.stabs "E:\\DEMO资料汇总\\CSU38F20\\CSU38F20 DEMO\\timer2\\",0x64,0,0,0
.stabs "E:\\DEMO资料汇总\\CSU38F20\\CSU38F20 DEMO\\timer2\\SysRegDefine.c",0x64,0,0,0
.stabs "int:t1=r1;-32768;32767;",0x80,0,0,0
.stabs "unsigned int:t2=r2;0;65535;",0x80,0,0,0
.stabs "long int:t3=r3;-2147483648;2147483647;",0x80,0,0,0
.stabs "unsigned long int:t4=r4;0;4294967295;",0x80,0,0,0
.stabs "long long unsigned int:t6=r6;0;4294967295;",0x80,0,0,0
.stabs "short int:t7=r7;-32768;32767;",0x80,0,0,0
.stabs "short unsigned int:t8=r8;0;65535;",0x80,0,0,0
.stabs "char:t9=r9;-128;127;",0x80,0,0,0
.stabs "unsigned char:t10=r10;0;255;",0x80,0,0,0
.stabs "_Bool:t11=r11;0;1;",0x80,0,0,0
.stabs "sbit:t12=r12;0;1;",0x80,0,0,0
.stabs "float:t13=r13;4;0;",0x80,0,0,0
.stabs "double:t14=r14;4;0;",0x80,0,0,0
.stabs "long double:t15=r15;4;0;",0x80,0,0,0
.stabs "void:t16=r10;0;255;",0x80,0,0,0
.stabs "IND0:G10;",0x20,0,0,_IND0
.stabs "FSR0:G10;",0x20,0,0,_FSR0
.stabs "STATUS:G10;",0x20,0,0,_STATUS
.stabs "WORK:G10;",0x20,0,0,_WORK
.stabs "INTF:G10;",0x20,0,0,_INTF
.stabs "INTE:G10;",0x20,0,0,_INTE
.stabs "BSK:G10;",0x20,0,0,_BSK
.stabs "RSTSR:G10;",0x20,0,0,_RSTSR
.stabs "EADRH:G10;",0x20,0,0,_EADRH
.stabs "EADRL:G10;",0x20,0,0,_EADRL
.stabs "EDATH:G10;",0x20,0,0,_EDATH
.stabs "WDTCON:G10;",0x20,0,0,_WDTCON
.stabs "WDTIN:G10;",0x20,0,0,_WDTIN
.stabs "TM0CON:G10;",0x20,0,0,_TM0CON
.stabs "TM0IN:G10;",0x20,0,0,_TM0IN
.stabs "TM0CNT:G10;",0x20,0,0,_TM0CNT
.stabs "PAGECTL:G10;",0x20,0,0,_PAGECTL
.stabs "MCK:G10;",0x20,0,0,_MCK
.stabs "TM2CON:G10;",0x20,0,0,_TM2CON
.stabs "TM2IN:G10;",0x20,0,0,_TM2IN
.stabs "TM2CNT:G10;",0x20,0,0,_TM2CNT
.stabs "TM2R:G10;",0x20,0,0,_TM2R
.stabs "TM3CON:G10;",0x20,0,0,_TM3CON
.stabs "TM3IN:G10;",0x20,0,0,_TM3IN
.stabs "TM3CNT:G10;",0x20,0,0,_TM3CNT
.stabs "TM3R:G10;",0x20,0,0,_TM3R
.stabs "TM3INH:G10;",0x20,0,0,_TM3INH
.stabs "PT1:G10;",0x20,0,0,_PT1
.stabs "PT1EN:G10;",0x20,0,0,_PT1EN
.stabs "PT1PU:G10;",0x20,0,0,_PT1PU
.stabs "PT1CON:G10;",0x20,0,0,_PT1CON
.stabs "TM2INH:G10;",0x20,0,0,_TM2INH
.stabs "TM2CNTH:G10;",0x20,0,0,_TM2CNTH
.stabs "TM2RH:G10;",0x20,0,0,_TM2RH
.stabs "TM3CNTH:G10;",0x20,0,0,_TM3CNTH
.stabs "PT3:G10;",0x20,0,0,_PT3
.stabs "PT3EN:G10;",0x20,0,0,_PT3EN
.stabs "PT3PU:G10;",0x20,0,0,_PT3PU
.stabs "PT3CON:G10;",0x20,0,0,_PT3CON
.stabs "TM3RH:G10;",0x20,0,0,_TM3RH
.stabs "TM3CON2:G10;",0x20,0,0,_TM3CON2
.stabs "CONFIG1:G10;",0x20,0,0,_CONFIG1
.stabs "CONFIG2:G10;",0x20,0,0,_CONFIG2
.stabs "PT5:G10;",0x20,0,0,_PT5
.stabs "PT5EN:G10;",0x20,0,0,_PT5EN
.stabs "PT5PU:G10;",0x20,0,0,_PT5PU
.stabs "PT5CON:G10;",0x20,0,0,_PT5CON
.stabs "SRADCON0:G10;",0x20,0,0,_SRADCON0
.stabs "SRADCON1:G10;",0x20,0,0,_SRADCON1
.stabs "SRADCON2:G10;",0x20,0,0,_SRADCON2
.stabs "SRADL:G10;",0x20,0,0,_SRADL
.stabs "SRADH:G10;",0x20,0,0,_SRADH
.stabs "SROFTL:G10;",0x20,0,0,_SROFTL
.stabs "SROFTH:G10;",0x20,0,0,_SROFTH
.stabs "INTF2:G10;",0x20,0,0,_INTF2
.stabs "INTE2:G10;",0x20,0,0,_INTE2
.stabs "INTCFG:G10;",0x20,0,0,_INTCFG
.stabs "PT1CON1:G10;",0x20,0,0,_PT1CON1
.stabs "PT5CON1:G10;",0x20,0,0,_PT5CON1
.stabs "TM3CON3:G10;",0x20,0,0,_TM3CON3
.stabs "WWDTCR:G10;",0x20,0,0,_WWDTCR
.stabs "WWDTWR:G10;",0x20,0,0,_WWDTWR
.stabs "UR0_CR1:G10;",0x20,0,0,_UR0_CR1
.stabs "UR0_BRR0:G10;",0x20,0,0,_UR0_BRR0
.stabs "UR0_BRR1:G10;",0x20,0,0,_UR0_BRR1
.stabs "UR0_TX_REG:G10;",0x20,0,0,_UR0_TX_REG
.stabs "UR0_RX_REG:G10;",0x20,0,0,_UR0_RX_REG
.stabs "UR0_ST:G10;",0x20,0,0,_UR0_ST
.stabs "UR0_INTF:G10;",0x20,0,0,_UR0_INTF
.stabs "UR0_INTE:G10;",0x20,0,0,_UR0_INTE
.stabs "I2CCON:G10;",0x20,0,0,_I2CCON
.stabs "I2CCON1:G10;",0x20,0,0,_I2CCON1
.stabs "I2CDAT:G10;",0x20,0,0,_I2CDAT
.stabs "I2CADR:G10;",0x20,0,0,_I2CADR
.stabs "I2C_INTF:G10;",0x20,0,0,_I2C_INTF
.stabs "I2C_INTE:G10;",0x20,0,0,_I2C_INTE
.stabs "ISPCON1:G10;",0x20,0,0,_ISPCON1
.stabs "WRPRT:G10;",0x20,0,0,_WRPRT
.stabs "TM4CON:G10;",0x20,0,0,_TM4CON
.stabs "TM4IN:G10;",0x20,0,0,_TM4IN
.stabs "TM4CNT:G10;",0x20,0,0,_TM4CNT
.stabs "TM4R:G10;",0x20,0,0,_TM4R
.stabs "TM4INH:G10;",0x20,0,0,_TM4INH
.stabs "TM4CNTH:G10;",0x20,0,0,_TM4CNTH
.stabs "TM4RH:G10;",0x20,0,0,_TM4RH
.stabs "LEDADR:G10;",0x20,0,0,_LEDADR
.stabs "LEDDAT:G10;",0x20,0,0,_LEDDAT
.stabs "LEDDUTY:G10;",0x20,0,0,_LEDDUTY
.stabs "LEDCOM:G10;",0x20,0,0,_LEDCOM
.stabs "LEDCON:G10;",0x20,0,0,_LEDCON
.stabs "LEDCON1:G10;",0x20,0,0,_LEDCON1
.stabs "CHPCON:G10;",0x20,0,0,_CHPCON
.stabs "TBLPEN:G10;",0x20,0,0,_TBLPEN
.stabs "LVDCON:G10;",0x20,0,0,_LVDCON
.stabs "MCK1:G10;",0x20,0,0,_MCK1
.stabs "PT5_BIGDRV:G10;",0x20,0,0,_PT5_BIGDRV
.stabs "CONFLASH:G10;",0x20,0,0,_CONFLASH
.stabs "Z:G12;",0x20,0,0,_Z
.stabs "C:G12;",0x20,0,0,_C
.stabs "DC:G12;",0x20,0,0,_DC
.stabs "TO:G12;",0x20,0,0,_TO
.stabs "PD:G12;",0x20,0,0,_PD
.stabs "E0IF:G12;",0x20,0,0,_E0IF
.stabs "E1IF:G12;",0x20,0,0,_E1IF
.stabs "SRADIF:G12;",0x20,0,0,_SRADIF
.stabs "TM0IF:G12;",0x20,0,0,_TM0IF
.stabs "TM2IF:G12;",0x20,0,0,_TM2IF
.stabs "E0IE:G12;",0x20,0,0,_E0IE
.stabs "E1IE:G12;",0x20,0,0,_E1IE
.stabs "SRADIE:G12;",0x20,0,0,_SRADIE
.stabs "TM0IE:G12;",0x20,0,0,_TM0IE
.stabs "TM2IE:G12;",0x20,0,0,_TM2IE
.stabs "GIE:G12;",0x20,0,0,_GIE
.stabs "PAGE_0:G12;",0x20,0,0,_PAGE_0
.stabs "IRP0:G12;",0x20,0,0,_IRP0
.stabs "WWDTF:G12;",0x20,0,0,_WWDTF
.stabs "ILOPF:G12;",0x20,0,0,_ILOPF
.stabs "EMCF:G12;",0x20,0,0,_EMCF
.stabs "EADR_8:G12;",0x20,0,0,_EADR_8
.stabs "EADR_9:G12;",0x20,0,0,_EADR_9
.stabs "EADR_10:G12;",0x20,0,0,_EADR_10
.stabs "EADR_11:G12;",0x20,0,0,_EADR_11
.stabs "EADR_12:G12;",0x20,0,0,_EADR_12
.stabs "EADR_13:G12;",0x20,0,0,_EADR_13
.stabs "EADR_14:G12;",0x20,0,0,_EADR_14
.stabs "EADR_15:G12;",0x20,0,0,_EADR_15
.stabs "EADR_0:G12;",0x20,0,0,_EADR_0
.stabs "EADR_1:G12;",0x20,0,0,_EADR_1
.stabs "EADR_2:G12;",0x20,0,0,_EADR_2
.stabs "EADR_3:G12;",0x20,0,0,_EADR_3
.stabs "EADR_4:G12;",0x20,0,0,_EADR_4
.stabs "EADR_5:G12;",0x20,0,0,_EADR_5
.stabs "EADR_6:G12;",0x20,0,0,_EADR_6
.stabs "EADR_7:G12;",0x20,0,0,_EADR_7
.stabs "EDATH_0:G12;",0x20,0,0,_EDATH_0
.stabs "EDATH_1:G12;",0x20,0,0,_EDATH_1
.stabs "EDATH_2:G12;",0x20,0,0,_EDATH_2
.stabs "EDATH_3:G12;",0x20,0,0,_EDATH_3
.stabs "EDATH_4:G12;",0x20,0,0,_EDATH_4
.stabs "EDATH_5:G12;",0x20,0,0,_EDATH_5
.stabs "EDATH_6:G12;",0x20,0,0,_EDATH_6
.stabs "EDATH_7:G12;",0x20,0,0,_EDATH_7
.stabs "WTS_0:G12;",0x20,0,0,_WTS_0
.stabs "WTS_1:G12;",0x20,0,0,_WTS_1
.stabs "WTS_2:G12;",0x20,0,0,_WTS_2
.stabs "WDTEN:G12;",0x20,0,0,_WDTEN
.stabs "WDTIN_0:G12;",0x20,0,0,_WDTIN_0
.stabs "WDTIN_1:G12;",0x20,0,0,_WDTIN_1
.stabs "WDTIN_2:G12;",0x20,0,0,_WDTIN_2
.stabs "WDTIN_3:G12;",0x20,0,0,_WDTIN_3
.stabs "WDTIN_4:G12;",0x20,0,0,_WDTIN_4
.stabs "WDTIN_5:G12;",0x20,0,0,_WDTIN_5
.stabs "WDTIN_6:G12;",0x20,0,0,_WDTIN_6
.stabs "WDTIN_7:G12;",0x20,0,0,_WDTIN_7
.stabs "T0SEL_0:G12;",0x20,0,0,_T0SEL_0
.stabs "T0SEL_1:G12;",0x20,0,0,_T0SEL_1
.stabs "T0RSTB:G12;",0x20,0,0,_T0RSTB
.stabs "T0RATE_0:G12;",0x20,0,0,_T0RATE_0
.stabs "T0RATE_1:G12;",0x20,0,0,_T0RATE_1
.stabs "T0RATE_2:G12;",0x20,0,0,_T0RATE_2
.stabs "T0EN:G12;",0x20,0,0,_T0EN
.stabs "TM0IN_0:G12;",0x20,0,0,_TM0IN_0
.stabs "TM0IN_1:G12;",0x20,0,0,_TM0IN_1
.stabs "TM0IN_2:G12;",0x20,0,0,_TM0IN_2
.stabs "TM0IN_3:G12;",0x20,0,0,_TM0IN_3
.stabs "TM0IN_4:G12;",0x20,0,0,_TM0IN_4
.stabs "TM0IN_5:G12;",0x20,0,0,_TM0IN_5
.stabs "TM0IN_6:G12;",0x20,0,0,_TM0IN_6
.stabs "TM0IN_7:G12;",0x20,0,0,_TM0IN_7
.stabs "TM0CNT_0:G12;",0x20,0,0,_TM0CNT_0
.stabs "TM0CNT_1:G12;",0x20,0,0,_TM0CNT_1
.stabs "TM0CNT_2:G12;",0x20,0,0,_TM0CNT_2
.stabs "TM0CNT_3:G12;",0x20,0,0,_TM0CNT_3
.stabs "TM0CNT_4:G12;",0x20,0,0,_TM0CNT_4
.stabs "TM0CNT_5:G12;",0x20,0,0,_TM0CNT_5
.stabs "TM0CNT_6:G12;",0x20,0,0,_TM0CNT_6
.stabs "TM0CNT_7:G12;",0x20,0,0,_TM0CNT_7
.stabs "PAGE2:G12;",0x20,0,0,_PAGE2
.stabs "CST_WDT:G12;",0x20,0,0,_CST_WDT
.stabs "PWM2OUT:G12;",0x20,0,0,_PWM2OUT
.stabs "T2OUT:G12;",0x20,0,0,_T2OUT
.stabs "T2RSTB:G12;",0x20,0,0,_T2RSTB
.stabs "T2CKS:G12;",0x20,0,0,_T2CKS
.stabs "T2RATE_0:G12;",0x20,0,0,_T2RATE_0
.stabs "T2RATE_1:G12;",0x20,0,0,_T2RATE_1
.stabs "T2RATE_2:G12;",0x20,0,0,_T2RATE_2
.stabs "T2EN:G12;",0x20,0,0,_T2EN
.stabs "TM2IN_0:G12;",0x20,0,0,_TM2IN_0
.stabs "TM2IN_1:G12;",0x20,0,0,_TM2IN_1
.stabs "TM2IN_2:G12;",0x20,0,0,_TM2IN_2
.stabs "TM2IN_3:G12;",0x20,0,0,_TM2IN_3
.stabs "TM2IN_4:G12;",0x20,0,0,_TM2IN_4
.stabs "TM2IN_5:G12;",0x20,0,0,_TM2IN_5
.stabs "TM2IN_6:G12;",0x20,0,0,_TM2IN_6
.stabs "TM2IN_7:G12;",0x20,0,0,_TM2IN_7
.stabs "TM2CNT_0:G12;",0x20,0,0,_TM2CNT_0
.stabs "TM2CNT_1:G12;",0x20,0,0,_TM2CNT_1
.stabs "TM2CNT_2:G12;",0x20,0,0,_TM2CNT_2
.stabs "TM2CNT_3:G12;",0x20,0,0,_TM2CNT_3
.stabs "TM2CNT_4:G12;",0x20,0,0,_TM2CNT_4
.stabs "TM2CNT_5:G12;",0x20,0,0,_TM2CNT_5
.stabs "TM2CNT_6:G12;",0x20,0,0,_TM2CNT_6
.stabs "TM2CNT_7:G12;",0x20,0,0,_TM2CNT_7
.stabs "TM2R_0:G12;",0x20,0,0,_TM2R_0
.stabs "TM2R_1:G12;",0x20,0,0,_TM2R_1
.stabs "TM2R_2:G12;",0x20,0,0,_TM2R_2
.stabs "TM2R_3:G12;",0x20,0,0,_TM2R_3
.stabs "TM2R_4:G12;",0x20,0,0,_TM2R_4
.stabs "TM2R_5:G12;",0x20,0,0,_TM2R_5
.stabs "TM2R_6:G12;",0x20,0,0,_TM2R_6
.stabs "TM2R_7:G12;",0x20,0,0,_TM2R_7
.stabs "PWM3OUT:G12;",0x20,0,0,_PWM3OUT
.stabs "T3OUT:G12;",0x20,0,0,_T3OUT
.stabs "T3RSTB:G12;",0x20,0,0,_T3RSTB
.stabs "T3CKS:G12;",0x20,0,0,_T3CKS
.stabs "T3RATE_0:G12;",0x20,0,0,_T3RATE_0
.stabs "T3RATE_1:G12;",0x20,0,0,_T3RATE_1
.stabs "T3RATE_2:G12;",0x20,0,0,_T3RATE_2
.stabs "T3EN:G12;",0x20,0,0,_T3EN
.stabs "TM3IN_0:G12;",0x20,0,0,_TM3IN_0
.stabs "TM3IN_1:G12;",0x20,0,0,_TM3IN_1
.stabs "TM3IN_2:G12;",0x20,0,0,_TM3IN_2
.stabs "TM3IN_3:G12;",0x20,0,0,_TM3IN_3
.stabs "TM3IN_4:G12;",0x20,0,0,_TM3IN_4
.stabs "TM3IN_5:G12;",0x20,0,0,_TM3IN_5
.stabs "TM3IN_6:G12;",0x20,0,0,_TM3IN_6
.stabs "TM3IN_7:G12;",0x20,0,0,_TM3IN_7
.stabs "TM3CNT_0:G12;",0x20,0,0,_TM3CNT_0
.stabs "TM3CNT_1:G12;",0x20,0,0,_TM3CNT_1
.stabs "TM3CNT_2:G12;",0x20,0,0,_TM3CNT_2
.stabs "TM3CNT_3:G12;",0x20,0,0,_TM3CNT_3
.stabs "TM3CNT_4:G12;",0x20,0,0,_TM3CNT_4
.stabs "TM3CNT_5:G12;",0x20,0,0,_TM3CNT_5
.stabs "TM3CNT_6:G12;",0x20,0,0,_TM3CNT_6
.stabs "TM3CNT_7:G12;",0x20,0,0,_TM3CNT_7
.stabs "TM3R_0:G12;",0x20,0,0,_TM3R_0
.stabs "TM3R_1:G12;",0x20,0,0,_TM3R_1
.stabs "TM3R_2:G12;",0x20,0,0,_TM3R_2
.stabs "TM3R_3:G12;",0x20,0,0,_TM3R_3
.stabs "TM3R_4:G12;",0x20,0,0,_TM3R_4
.stabs "TM3R_5:G12;",0x20,0,0,_TM3R_5
.stabs "TM3R_6:G12;",0x20,0,0,_TM3R_6
.stabs "TM3R_7:G12;",0x20,0,0,_TM3R_7
.stabs "TM3INH_8:G12;",0x20,0,0,_TM3INH_8
.stabs "TM3INH_9:G12;",0x20,0,0,_TM3INH_9
.stabs "TM3INH_10:G12;",0x20,0,0,_TM3INH_10
.stabs "TM3INH_11:G12;",0x20,0,0,_TM3INH_11
.stabs "PT1_0:G12;",0x20,0,0,_PT1_0
.stabs "PT1_3:G12;",0x20,0,0,_PT1_3
.stabs "PT1_4:G12;",0x20,0,0,_PT1_4
.stabs "PT1_5:G12;",0x20,0,0,_PT1_5
.stabs "PT1EN_0:G12;",0x20,0,0,_PT1EN_0
.stabs "PT1EN_3:G12;",0x20,0,0,_PT1EN_3
.stabs "PT1EN_4:G12;",0x20,0,0,_PT1EN_4
.stabs "PT1EN_5:G12;",0x20,0,0,_PT1EN_5
.stabs "PT1PU_0:G12;",0x20,0,0,_PT1PU_0
.stabs "PT1PU_3:G12;",0x20,0,0,_PT1PU_3
.stabs "PT1PU_4:G12;",0x20,0,0,_PT1PU_4
.stabs "PT1PU_5:G12;",0x20,0,0,_PT1PU_5
.stabs "E0M_0:G12;",0x20,0,0,_E0M_0
.stabs "E0M_1:G12;",0x20,0,0,_E0M_1
.stabs "E1M:G12;",0x20,0,0,_E1M
.stabs "PT1W_0:G12;",0x20,0,0,_PT1W_0
.stabs "PT1W_1:G12;",0x20,0,0,_PT1W_1
.stabs "PT1W_2:G12;",0x20,0,0,_PT1W_2
.stabs "TM2IN_8:G12;",0x20,0,0,_TM2IN_8
.stabs "TM2IN_9:G12;",0x20,0,0,_TM2IN_9
.stabs "TM2IN_10:G12;",0x20,0,0,_TM2IN_10
.stabs "TM2IN_11:G12;",0x20,0,0,_TM2IN_11
.stabs "TM2CNT_8:G12;",0x20,0,0,_TM2CNT_8
.stabs "TM2CNT_9:G12;",0x20,0,0,_TM2CNT_9
.stabs "TM2CNT_10:G12;",0x20,0,0,_TM2CNT_10
.stabs "TM2CNT_11:G12;",0x20,0,0,_TM2CNT_11
.stabs "TM2R_8:G12;",0x20,0,0,_TM2R_8
.stabs "TM2R_9:G12;",0x20,0,0,_TM2R_9
.stabs "TM2R_10:G12;",0x20,0,0,_TM2R_10
.stabs "TM2R_11:G12;",0x20,0,0,_TM2R_11
.stabs "TM3CNT_8:G12;",0x20,0,0,_TM3CNT_8
.stabs "TM3CNT_9:G12;",0x20,0,0,_TM3CNT_9
.stabs "TM3CNT_10:G12;",0x20,0,0,_TM3CNT_10
.stabs "TM3CNT_11:G12;",0x20,0,0,_TM3CNT_11
.stabs "PT3_0:G12;",0x20,0,0,_PT3_0
.stabs "PT3_1:G12;",0x20,0,0,_PT3_1
.stabs "PT3_2:G12;",0x20,0,0,_PT3_2
.stabs "PT3_3:G12;",0x20,0,0,_PT3_3
.stabs "PT3_4:G12;",0x20,0,0,_PT3_4
.stabs "PT3_5:G12;",0x20,0,0,_PT3_5
.stabs "PT3_6:G12;",0x20,0,0,_PT3_6
.stabs "PT3EN_0:G12;",0x20,0,0,_PT3EN_0
.stabs "PT3EN_1:G12;",0x20,0,0,_PT3EN_1
.stabs "PT3EN_2:G12;",0x20,0,0,_PT3EN_2
.stabs "PT3EN_3:G12;",0x20,0,0,_PT3EN_3
.stabs "PT3EN_4:G12;",0x20,0,0,_PT3EN_4
.stabs "PT3EN_5:G12;",0x20,0,0,_PT3EN_5
.stabs "PT3EN_6:G12;",0x20,0,0,_PT3EN_6
.stabs "PT3PU_0:G12;",0x20,0,0,_PT3PU_0
.stabs "PT3PU_1:G12;",0x20,0,0,_PT3PU_1
.stabs "PT3PU_2:G12;",0x20,0,0,_PT3PU_2
.stabs "PT3PU_3:G12;",0x20,0,0,_PT3PU_3
.stabs "PT3PU_4:G12;",0x20,0,0,_PT3PU_4
.stabs "PT3PU_5:G12;",0x20,0,0,_PT3PU_5
.stabs "PT3PU_6:G12;",0x20,0,0,_PT3PU_6
.stabs "PT3CON_0:G12;",0x20,0,0,_PT3CON_0
.stabs "PT3CON_1:G12;",0x20,0,0,_PT3CON_1
.stabs "PT3CON_2:G12;",0x20,0,0,_PT3CON_2
.stabs "PT3CON_3:G12;",0x20,0,0,_PT3CON_3
.stabs "PT3CON_4:G12;",0x20,0,0,_PT3CON_4
.stabs "PT3CON_5:G12;",0x20,0,0,_PT3CON_5
.stabs "PT3CON_6:G12;",0x20,0,0,_PT3CON_6
.stabs "TM3R_8:G12;",0x20,0,0,_TM3R_8
.stabs "TM3R_9:G12;",0x20,0,0,_TM3R_9
.stabs "TM3R_10:G12;",0x20,0,0,_TM3R_10
.stabs "TM3R_11:G12;",0x20,0,0,_TM3R_11
.stabs "P3L_OEN:G12;",0x20,0,0,_P3L_OEN
.stabs "P3H_OEN:G12;",0x20,0,0,_P3H_OEN
.stabs "DT3_EN:G12;",0x20,0,0,_DT3_EN
.stabs "DT3CNT_0:G12;",0x20,0,0,_DT3CNT_0
.stabs "DT3CNT_1:G12;",0x20,0,0,_DT3CNT_1
.stabs "DT3CNT_2:G12;",0x20,0,0,_DT3CNT_2
.stabs "DT3CK_0:G12;",0x20,0,0,_DT3CK_0
.stabs "DT3CK_1:G12;",0x20,0,0,_DT3CK_1
.stabs "PWM2PO:G12;",0x20,0,0,_PWM2PO
.stabs "PWM2STALL:G12;",0x20,0,0,_PWM2STALL
.stabs "PWM3STALL:G12;",0x20,0,0,_PWM3STALL
.stabs "PWM4STALL:G12;",0x20,0,0,_PWM4STALL
.stabs "P3LINV:G12;",0x20,0,0,_P3LINV
.stabs "P3HINV:G12;",0x20,0,0,_P3HINV
.stabs "T4RATE_3:G12;",0x20,0,0,_T4RATE_3
.stabs "T2RATE_3:G12;",0x20,0,0,_T2RATE_3
.stabs "T3RATE_3:G12;",0x20,0,0,_T3RATE_3
.stabs "PWMIS:G12;",0x20,0,0,_PWMIS
.stabs "VTHSEL:G12;",0x20,0,0,_VTHSEL
.stabs "PT5_0:G12;",0x20,0,0,_PT5_0
.stabs "PT5_1:G12;",0x20,0,0,_PT5_1
.stabs "PT5_2:G12;",0x20,0,0,_PT5_2
.stabs "PT5_3:G12;",0x20,0,0,_PT5_3
.stabs "PT5_4:G12;",0x20,0,0,_PT5_4
.stabs "PT5_5:G12;",0x20,0,0,_PT5_5
.stabs "PT5_6:G12;",0x20,0,0,_PT5_6
.stabs "PT5_7:G12;",0x20,0,0,_PT5_7
.stabs "PT5EN_0:G12;",0x20,0,0,_PT5EN_0
.stabs "PT5EN_1:G12;",0x20,0,0,_PT5EN_1
.stabs "PT5EN_2:G12;",0x20,0,0,_PT5EN_2
.stabs "PT5EN_3:G12;",0x20,0,0,_PT5EN_3
.stabs "PT5EN_4:G12;",0x20,0,0,_PT5EN_4
.stabs "PT5EN_5:G12;",0x20,0,0,_PT5EN_5
.stabs "PT5EN_6:G12;",0x20,0,0,_PT5EN_6
.stabs "PT5EN_7:G12;",0x20,0,0,_PT5EN_7
.stabs "PT5PU_0:G12;",0x20,0,0,_PT5PU_0
.stabs "PT5PU_1:G12;",0x20,0,0,_PT5PU_1
.stabs "PT5PU_2:G12;",0x20,0,0,_PT5PU_2
.stabs "PT5PU_3:G12;",0x20,0,0,_PT5PU_3
.stabs "PT5PU_4:G12;",0x20,0,0,_PT5PU_4
.stabs "PT5PU_5:G12;",0x20,0,0,_PT5PU_5
.stabs "PT5PU_6:G12;",0x20,0,0,_PT5PU_6
.stabs "PT5PU_7:G12;",0x20,0,0,_PT5PU_7
.stabs "PT5CON_0:G12;",0x20,0,0,_PT5CON_0
.stabs "PT5CON_1:G12;",0x20,0,0,_PT5CON_1
.stabs "PT5CON_2:G12;",0x20,0,0,_PT5CON_2
.stabs "PT5CON_3:G12;",0x20,0,0,_PT5CON_3
.stabs "PT5CON_4:G12;",0x20,0,0,_PT5CON_4
.stabs "PT5CON_5:G12;",0x20,0,0,_PT5CON_5
.stabs "PT5CON_6:G12;",0x20,0,0,_PT5CON_6
.stabs "PT5CON_7:G12;",0x20,0,0,_PT5CON_7
.stabs "SRADCKS_0:G12;",0x20,0,0,_SRADCKS_0
.stabs "SRADCKS_1:G12;",0x20,0,0,_SRADCKS_1
.stabs "SRADACKS_0:G12;",0x20,0,0,_SRADACKS_0
.stabs "SRADACKS_1:G12;",0x20,0,0,_SRADACKS_1
.stabs "SARVCMSEL:G12;",0x20,0,0,_SARVCMSEL
.stabs "VREFS_0:G12;",0x20,0,0,_VREFS_0
.stabs "VREFS_1:G12;",0x20,0,0,_VREFS_1
.stabs "OFFEX:G12;",0x20,0,0,_OFFEX
.stabs "ENOV:G12;",0x20,0,0,_ENOV
.stabs "CALIF:G12;",0x20,0,0,_CALIF
.stabs "OFTEN:G12;",0x20,0,0,_OFTEN
.stabs "SRADS:G12;",0x20,0,0,_SRADS
.stabs "SRADEN:G12;",0x20,0,0,_SRADEN
.stabs "SAR_DIFFEN:G12;",0x20,0,0,_SAR_DIFFEN
.stabs "CHS_0:G12;",0x20,0,0,_CHS_0
.stabs "CHS_1:G12;",0x20,0,0,_CHS_1
.stabs "CHS_2:G12;",0x20,0,0,_CHS_2
.stabs "CHS_3:G12;",0x20,0,0,_CHS_3
.stabs "SRAD_0:G12;",0x20,0,0,_SRAD_0
.stabs "SRAD_1:G12;",0x20,0,0,_SRAD_1
.stabs "SRAD_2:G12;",0x20,0,0,_SRAD_2
.stabs "SRAD_3:G12;",0x20,0,0,_SRAD_3
.stabs "SRAD_4:G12;",0x20,0,0,_SRAD_4
.stabs "SRAD_5:G12;",0x20,0,0,_SRAD_5
.stabs "SRAD_6:G12;",0x20,0,0,_SRAD_6
.stabs "SRAD_7:G12;",0x20,0,0,_SRAD_7
.stabs "SRAD_8:G12;",0x20,0,0,_SRAD_8
.stabs "SRAD_9:G12;",0x20,0,0,_SRAD_9
.stabs "SRAD_10:G12;",0x20,0,0,_SRAD_10
.stabs "SRAD_11:G12;",0x20,0,0,_SRAD_11
.stabs "SROFT_0:G12;",0x20,0,0,_SROFT_0
.stabs "SROFT_1:G12;",0x20,0,0,_SROFT_1
.stabs "SROFT_2:G12;",0x20,0,0,_SROFT_2
.stabs "SROFT_3:G12;",0x20,0,0,_SROFT_3
.stabs "SROFT_4:G12;",0x20,0,0,_SROFT_4
.stabs "SROFT_5:G12;",0x20,0,0,_SROFT_5
.stabs "SROFT_6:G12;",0x20,0,0,_SROFT_6
.stabs "SROFT_7:G12;",0x20,0,0,_SROFT_7
.stabs "SROFT_8:G12;",0x20,0,0,_SROFT_8
.stabs "SROFT_9:G12;",0x20,0,0,_SROFT_9
.stabs "SROFT_10:G12;",0x20,0,0,_SROFT_10
.stabs "SROFT_11:G12;",0x20,0,0,_SROFT_11
.stabs "UR0IF:G12;",0x20,0,0,_UR0IF
.stabs "I2CIF:G12;",0x20,0,0,_I2CIF
.stabs "LVDIF:G12;",0x20,0,0,_LVDIF
.stabs "TM4IF:G12;",0x20,0,0,_TM4IF
.stabs "TM3IF:G12;",0x20,0,0,_TM3IF
.stabs "LVDIE:G12;",0x20,0,0,_LVDIE
.stabs "TM4IE:G12;",0x20,0,0,_TM4IE
.stabs "TM3IE:G12;",0x20,0,0,_TM3IE
.stabs "INTCFG_0:G12;",0x20,0,0,_INTCFG_0
.stabs "INTCFG_1:G12;",0x20,0,0,_INTCFG_1
.stabs "INTCFG_2:G12;",0x20,0,0,_INTCFG_2
.stabs "INTCFG_3:G12;",0x20,0,0,_INTCFG_3
.stabs "INTCFG_4:G12;",0x20,0,0,_INTCFG_4
.stabs "INTCFG_5:G12;",0x20,0,0,_INTCFG_5
.stabs "INTCFG_6:G12;",0x20,0,0,_INTCFG_6
.stabs "INTCFG_7:G12;",0x20,0,0,_INTCFG_7
.stabs "PT1CON0:G12;",0x20,0,0,_PT1CON0
.stabs "PT5W_5:G12;",0x20,0,0,_PT5W_5
.stabs "PT5W_6:G12;",0x20,0,0,_PT5W_6
.stabs "PT5W_7:G12;",0x20,0,0,_PT5W_7
.stabs "P3L2OEN:G12;",0x20,0,0,_P3L2OEN
.stabs "P3H2OEN:G12;",0x20,0,0,_P3H2OEN
.stabs "P3L2INV:G12;",0x20,0,0,_P3L2INV
.stabs "P3H2INV:G12;",0x20,0,0,_P3H2INV
.stabs "PWM3PO:G12;",0x20,0,0,_PWM3PO
.stabs "TR_0:G12;",0x20,0,0,_TR_0
.stabs "TR_1:G12;",0x20,0,0,_TR_1
.stabs "TR_2:G12;",0x20,0,0,_TR_2
.stabs "TR_3:G12;",0x20,0,0,_TR_3
.stabs "TR_4:G12;",0x20,0,0,_TR_4
.stabs "TR_5:G12;",0x20,0,0,_TR_5
.stabs "TR_6:G12;",0x20,0,0,_TR_6
.stabs "WWDTEN:G12;",0x20,0,0,_WWDTEN
.stabs "WD_0:G12;",0x20,0,0,_WD_0
.stabs "WD_1:G12;",0x20,0,0,_WD_1
.stabs "WD_2:G12;",0x20,0,0,_WD_2
.stabs "WD_3:G12;",0x20,0,0,_WD_3
.stabs "WD_4:G12;",0x20,0,0,_WD_4
.stabs "WD_5:G12;",0x20,0,0,_WD_5
.stabs "WD_6:G12;",0x20,0,0,_WD_6
.stabs "UART0_EN:G12;",0x20,0,0,_UART0_EN
.stabs "UART0_SEL:G12;",0x20,0,0,_UART0_SEL
.stabs "TX_EN:G12;",0x20,0,0,_TX_EN
.stabs "RX_EN:G12;",0x20,0,0,_RX_EN
.stabs "RX9_EN:G12;",0x20,0,0,_RX9_EN
.stabs "TX9_EN:G12;",0x20,0,0,_TX9_EN
.stabs "RX9D:G12;",0x20,0,0,_RX9D
.stabs "TX9D:G12;",0x20,0,0,_TX9D
.stabs "BRR0_0:G12;",0x20,0,0,_BRR0_0
.stabs "BRR0_1:G12;",0x20,0,0,_BRR0_1
.stabs "BRR0_2:G12;",0x20,0,0,_BRR0_2
.stabs "BRR0_3:G12;",0x20,0,0,_BRR0_3
.stabs "BRR0_4:G12;",0x20,0,0,_BRR0_4
.stabs "BRR0_5:G12;",0x20,0,0,_BRR0_5
.stabs "BRR0_6:G12;",0x20,0,0,_BRR0_6
.stabs "BRR0_7:G12;",0x20,0,0,_BRR0_7
.stabs "BRR1_0:G12;",0x20,0,0,_BRR1_0
.stabs "BRR1_1:G12;",0x20,0,0,_BRR1_1
.stabs "BRR1_2:G12;",0x20,0,0,_BRR1_2
.stabs "BRR1_3:G12;",0x20,0,0,_BRR1_3
.stabs "UARTDIV_0:G12;",0x20,0,0,_UARTDIV_0
.stabs "UARTDIV_1:G12;",0x20,0,0,_UARTDIV_1
.stabs "UARTDIV_2:G12;",0x20,0,0,_UARTDIV_2
.stabs "TX_REG_0:G12;",0x20,0,0,_TX_REG_0
.stabs "TX_REG_1:G12;",0x20,0,0,_TX_REG_1
.stabs "TX_REG_2:G12;",0x20,0,0,_TX_REG_2
.stabs "TX_REG_3:G12;",0x20,0,0,_TX_REG_3
.stabs "TX_REG_4:G12;",0x20,0,0,_TX_REG_4
.stabs "TX_REG_5:G12;",0x20,0,0,_TX_REG_5
.stabs "TX_REG_6:G12;",0x20,0,0,_TX_REG_6
.stabs "TX_REG_7:G12;",0x20,0,0,_TX_REG_7
.stabs "RX_REG_0:G12;",0x20,0,0,_RX_REG_0
.stabs "RX_REG_1:G12;",0x20,0,0,_RX_REG_1
.stabs "RX_REG_2:G12;",0x20,0,0,_RX_REG_2
.stabs "RX_REG_3:G12;",0x20,0,0,_RX_REG_3
.stabs "RX_REG_4:G12;",0x20,0,0,_RX_REG_4
.stabs "RX_REG_5:G12;",0x20,0,0,_RX_REG_5
.stabs "RX_REG_6:G12;",0x20,0,0,_RX_REG_6
.stabs "RX_REG_7:G12;",0x20,0,0,_RX_REG_7
.stabs "STOP_ERR:G12;",0x20,0,0,_STOP_ERR
.stabs "RX_OV_ERR:G12;",0x20,0,0,_RX_OV_ERR
.stabs "TX_BUSY:G12;",0x20,0,0,_TX_BUSY
.stabs "RX_BUSY:G12;",0x20,0,0,_RX_BUSY
.stabs "TXFIFO_EMPTY:G12;",0x20,0,0,_TXFIFO_EMPTY
.stabs "UR_RINV:G12;",0x20,0,0,_UR_RINV
.stabs "UR_TINV:G12;",0x20,0,0,_UR_TINV
.stabs "UR0_TEIF:G12;",0x20,0,0,_UR0_TEIF
.stabs "UR0WK_IF:G12;",0x20,0,0,_UR0WK_IF
.stabs "UR0_RNIF:G12;",0x20,0,0,_UR0_RNIF
.stabs "UR0_RHIF:G12;",0x20,0,0,_UR0_RHIF
.stabs "UR0ERRIF:G12;",0x20,0,0,_UR0ERRIF
.stabs "UR0_TEIE:G12;",0x20,0,0,_UR0_TEIE
.stabs "UR0WK_IE:G12;",0x20,0,0,_UR0WK_IE
.stabs "UR0_RNIE:G12;",0x20,0,0,_UR0_RNIE
.stabs "UR0_RHIE:G12;",0x20,0,0,_UR0_RHIE
.stabs "UR0ERRIE:G12;",0x20,0,0,_UR0ERRIE
.stabs "I2CSTUS_0:G12;",0x20,0,0,_I2CSTUS_0
.stabs "I2CSTUS_1:G12;",0x20,0,0,_I2CSTUS_1
.stabs "I2CSTUS_2:G12;",0x20,0,0,_I2CSTUS_2
.stabs "I2CSTUS_3:G12;",0x20,0,0,_I2CSTUS_3
.stabs "ACK_EN:G12;",0x20,0,0,_ACK_EN
.stabs "CST_EN:G12;",0x20,0,0,_CST_EN
.stabs "AWK_EN:G12;",0x20,0,0,_AWK_EN
.stabs "I2C_EN:G12;",0x20,0,0,_I2C_EN
.stabs "I2C_DIV_0:G12;",0x20,0,0,_I2C_DIV_0
.stabs "I2C_DIV_1:G12;",0x20,0,0,_I2C_DIV_1
.stabs "I2C_SEL:G12;",0x20,0,0,_I2C_SEL
.stabs "I2CDAT_0:G12;",0x20,0,0,_I2CDAT_0
.stabs "I2CDAT_1:G12;",0x20,0,0,_I2CDAT_1
.stabs "I2CDAT_2:G12;",0x20,0,0,_I2CDAT_2
.stabs "I2CDAT_3:G12;",0x20,0,0,_I2CDAT_3
.stabs "I2CDAT_4:G12;",0x20,0,0,_I2CDAT_4
.stabs "I2CDAT_5:G12;",0x20,0,0,_I2CDAT_5
.stabs "I2CDAT_6:G12;",0x20,0,0,_I2CDAT_6
.stabs "I2CDAT_7:G12;",0x20,0,0,_I2CDAT_7
.stabs "GC_EN:G12;",0x20,0,0,_GC_EN
.stabs "I2CADR_0:G12;",0x20,0,0,_I2CADR_0
.stabs "I2CADR_1:G12;",0x20,0,0,_I2CADR_1
.stabs "I2CADR_2:G12;",0x20,0,0,_I2CADR_2
.stabs "I2CADR_3:G12;",0x20,0,0,_I2CADR_3
.stabs "I2CADR_4:G12;",0x20,0,0,_I2CADR_4
.stabs "I2CADR_5:G12;",0x20,0,0,_I2CADR_5
.stabs "I2CADR_6:G12;",0x20,0,0,_I2CADR_6
.stabs "I2C_STIF:G12;",0x20,0,0,_I2C_STIF
.stabs "I2C_RIF:G12;",0x20,0,0,_I2C_RIF
.stabs "I2C_TIF:G12;",0x20,0,0,_I2C_TIF
.stabs "I2C_STIE:G12;",0x20,0,0,_I2C_STIE
.stabs "I2C_RIE:G12;",0x20,0,0,_I2C_RIE
.stabs "I2C_TIE:G12;",0x20,0,0,_I2C_TIE
.stabs "ISPOF:G12;",0x20,0,0,_ISPOF
.stabs "ISPWDTRF:G12;",0x20,0,0,_ISPWDTRF
.stabs "WRPRTF:G12;",0x20,0,0,_WRPRTF
.stabs "PWM4OUT:G12;",0x20,0,0,_PWM4OUT
.stabs "T4OUT:G12;",0x20,0,0,_T4OUT
.stabs "T4RSTB:G12;",0x20,0,0,_T4RSTB
.stabs "T4CKS:G12;",0x20,0,0,_T4CKS
.stabs "T4RATE_0:G12;",0x20,0,0,_T4RATE_0
.stabs "T4RATE_1:G12;",0x20,0,0,_T4RATE_1
.stabs "T4RATE_2:G12;",0x20,0,0,_T4RATE_2
.stabs "T4EN:G12;",0x20,0,0,_T4EN
.stabs "TM4IN_0:G12;",0x20,0,0,_TM4IN_0
.stabs "TM4IN_1:G12;",0x20,0,0,_TM4IN_1
.stabs "TM4IN_2:G12;",0x20,0,0,_TM4IN_2
.stabs "TM4IN_3:G12;",0x20,0,0,_TM4IN_3
.stabs "TM4IN_4:G12;",0x20,0,0,_TM4IN_4
.stabs "TM4IN_5:G12;",0x20,0,0,_TM4IN_5
.stabs "TM4IN_6:G12;",0x20,0,0,_TM4IN_6
.stabs "TM4IN_7:G12;",0x20,0,0,_TM4IN_7
.stabs "TM4CNT_0:G12;",0x20,0,0,_TM4CNT_0
.stabs "TM4CNT_1:G12;",0x20,0,0,_TM4CNT_1
.stabs "TM4CNT_2:G12;",0x20,0,0,_TM4CNT_2
.stabs "TM4CNT_3:G12;",0x20,0,0,_TM4CNT_3
.stabs "TM4CNT_4:G12;",0x20,0,0,_TM4CNT_4
.stabs "TM4CNT_5:G12;",0x20,0,0,_TM4CNT_5
.stabs "TM4CNT_6:G12;",0x20,0,0,_TM4CNT_6
.stabs "TM4CNT_7:G12;",0x20,0,0,_TM4CNT_7
.stabs "TM4R_0:G12;",0x20,0,0,_TM4R_0
.stabs "TM4R_1:G12;",0x20,0,0,_TM4R_1
.stabs "TM4R_2:G12;",0x20,0,0,_TM4R_2
.stabs "TM4R_3:G12;",0x20,0,0,_TM4R_3
.stabs "TM4R_4:G12;",0x20,0,0,_TM4R_4
.stabs "TM4R_5:G12;",0x20,0,0,_TM4R_5
.stabs "TM4R_6:G12;",0x20,0,0,_TM4R_6
.stabs "TM4R_7:G12;",0x20,0,0,_TM4R_7
.stabs "TM4IN_8:G12;",0x20,0,0,_TM4IN_8
.stabs "TM4IN_9:G12;",0x20,0,0,_TM4IN_9
.stabs "TM4IN_10:G12;",0x20,0,0,_TM4IN_10
.stabs "TM4IN_11:G12;",0x20,0,0,_TM4IN_11
.stabs "TM4CNT_8:G12;",0x20,0,0,_TM4CNT_8
.stabs "TM4CNT_9:G12;",0x20,0,0,_TM4CNT_9
.stabs "TM4CNT_10:G12;",0x20,0,0,_TM4CNT_10
.stabs "TM4CNT_11:G12;",0x20,0,0,_TM4CNT_11
.stabs "TM4R_8:G12;",0x20,0,0,_TM4R_8
.stabs "TM4R_9:G12;",0x20,0,0,_TM4R_9
.stabs "TM4R_10:G12;",0x20,0,0,_TM4R_10
.stabs "TM4R_11:G12;",0x20,0,0,_TM4R_11
.stabs "LEDADR_0:G12;",0x20,0,0,_LEDADR_0
.stabs "LEDADR_1:G12;",0x20,0,0,_LEDADR_1
.stabs "LEDADR_2:G12;",0x20,0,0,_LEDADR_2
.stabs "LEDDAT_0:G12;",0x20,0,0,_LEDDAT_0
.stabs "LEDDAT_1:G12;",0x20,0,0,_LEDDAT_1
.stabs "LEDDAT_2:G12;",0x20,0,0,_LEDDAT_2
.stabs "LEDDAT_3:G12;",0x20,0,0,_LEDDAT_3
.stabs "LEDDAT_4:G12;",0x20,0,0,_LEDDAT_4
.stabs "LEDDAT_5:G12;",0x20,0,0,_LEDDAT_5
.stabs "LEDDAT_6:G12;",0x20,0,0,_LEDDAT_6
.stabs "LEDDAT_7:G12;",0x20,0,0,_LEDDAT_7
.stabs "LEDDUTY_0:G12;",0x20,0,0,_LEDDUTY_0
.stabs "LEDDUTY_1:G12;",0x20,0,0,_LEDDUTY_1
.stabs "LEDDUTY_2:G12;",0x20,0,0,_LEDDUTY_2
.stabs "LEDDUTY_3:G12;",0x20,0,0,_LEDDUTY_3
.stabs "LEDDUTY_4:G12;",0x20,0,0,_LEDDUTY_4
.stabs "LEDCOM_0:G12;",0x20,0,0,_LEDCOM_0
.stabs "LEDCOM_1:G12;",0x20,0,0,_LEDCOM_1
.stabs "LEDCOM_2:G12;",0x20,0,0,_LEDCOM_2
.stabs "LEDCOM_3:G12;",0x20,0,0,_LEDCOM_3
.stabs "LEDCOM_4:G12;",0x20,0,0,_LEDCOM_4
.stabs "LEDCOM_5:G12;",0x20,0,0,_LEDCOM_5
.stabs "LEDCOM_6:G12;",0x20,0,0,_LEDCOM_6
.stabs "LEDCOM_7:G12;",0x20,0,0,_LEDCOM_7
.stabs "LEDNUM_0:G12;",0x20,0,0,_LEDNUM_0
.stabs "LEDNUM_1:G12;",0x20,0,0,_LEDNUM_1
.stabs "LEDAUTO:G12;",0x20,0,0,_LEDAUTO
.stabs "LEDCKS_0:G12;",0x20,0,0,_LEDCKS_0
.stabs "LEDCKS_1:G12;",0x20,0,0,_LEDCKS_1
.stabs "LEDEN:G12;",0x20,0,0,_LEDEN
.stabs "LEDCUR_0:G12;",0x20,0,0,_LEDCUR_0
.stabs "LEDCUR_1:G12;",0x20,0,0,_LEDCUR_1
.stabs "CHPBYPSS:G12;",0x20,0,0,_CHPBYPSS
.stabs "CHPEN:G12;",0x20,0,0,_CHPEN
.stabs "CHIPCLKSEL_0:G12;",0x20,0,0,_CHIPCLKSEL_0
.stabs "CHIPCLKSEL_1:G12;",0x20,0,0,_CHIPCLKSEL_1
.stabs "TBLPEN_0:G12;",0x20,0,0,_TBLPEN_0
.stabs "TBLPEN_1:G12;",0x20,0,0,_TBLPEN_1
.stabs "TBLPEN_2:G12;",0x20,0,0,_TBLPEN_2
.stabs "TBLPEN_3:G12;",0x20,0,0,_TBLPEN_3
.stabs "TBLPEN_4:G12;",0x20,0,0,_TBLPEN_4
.stabs "TBLPEN_5:G12;",0x20,0,0,_TBLPEN_5
.stabs "TBLPEN_6:G12;",0x20,0,0,_TBLPEN_6
.stabs "TBLPEN_7:G12;",0x20,0,0,_TBLPEN_7
.stabs "LVD_SEL_0:G12;",0x20,0,0,_LVD_SEL_0
.stabs "LVD_SEL_1:G12;",0x20,0,0,_LVD_SEL_1
.stabs "LVD_SEL_2:G12;",0x20,0,0,_LVD_SEL_2
.stabs "LVDF:G12;",0x20,0,0,_LVDF
.stabs "LVDEN:G12;",0x20,0,0,_LVDEN
.stabs "MCK1_0:G12;",0x20,0,0,_MCK1_0
.stabs "MCK1_1:G12;",0x20,0,0,_MCK1_1
.stabs "MCK1_2:G12;",0x20,0,0,_MCK1_2
.stabs "MCK1_3:G12;",0x20,0,0,_MCK1_3
.stabs "PT5_BIGDRV_0:G12;",0x20,0,0,_PT5_BIGDRV_0
.stabs "PT5_BIGDRV_1:G12;",0x20,0,0,_PT5_BIGDRV_1
.stabs "PT5_BIGDRV_2:G12;",0x20,0,0,_PT5_BIGDRV_2
.stabs "PT5_BIGDRV_3:G12;",0x20,0,0,_PT5_BIGDRV_3
.stabs "PT5_BIGDRV_4:G12;",0x20,0,0,_PT5_BIGDRV_4
.stabs "PT5_BIGDRV_5:G12;",0x20,0,0,_PT5_BIGDRV_5
.stabs "PT5_BIGDRV_6:G12;",0x20,0,0,_PT5_BIGDRV_6
.stabs "PT5_BIGDRV_7:G12;",0x20,0,0,_PT5_BIGDRV_7
.stabs "CONFLASH_0:G12;",0x20,0,0,_CONFLASH_0
.stabs "CONFLASH_1:G12;",0x20,0,0,_CONFLASH_1
.stabs "CONFLASH_2:G12;",0x20,0,0,_CONFLASH_2
.stabs "CONFLASH_3:G12;",0x20,0,0,_CONFLASH_3
.stabs "CONFLASH_4:G12;",0x20,0,0,_CONFLASH_4
.stabs "CONFLASH_5:G12;",0x20,0,0,_CONFLASH_5
.include "csccCond.inc"
.include "csccCmp.inc"
.include "csccShift.inc"

	_IND0_SysRegDefine.c .section bank0,addr=0
	_IND0 .ds 1
	.ends

	_FSR0_SysRegDefine.c .section bank0,addr=2
	_FSR0 .ds 1
	.ends

	_STATUS_SysRegDefine.c .section bank0,addr=4
	_STATUS .ds 1
	.ends

	_WORK_SysRegDefine.c .section bank0,addr=5
	_WORK .ds 1
	.ends

	_INTF_SysRegDefine.c .section bank0,addr=6
	_INTF .ds 1
	.ends

	_INTE_SysRegDefine.c .section bank0,addr=7
	_INTE .ds 1
	.ends

	_BSK_SysRegDefine.c .section bank0,addr=8
	_BSK .ds 1
	.ends

	_RSTSR_SysRegDefine.c .section bank0,addr=9
	_RSTSR .ds 1
	.ends

	_EADRH_SysRegDefine.c .section bank0,addr=10
	_EADRH .ds 1
	.ends

	_EADRL_SysRegDefine.c .section bank0,addr=11
	_EADRL .ds 1
	.ends

	_EDATH_SysRegDefine.c .section bank0,addr=12
	_EDATH .ds 1
	.ends

	_WDTCON_SysRegDefine.c .section bank0,addr=13
	_WDTCON .ds 1
	.ends

	_WDTIN_SysRegDefine.c .section bank0,addr=14
	_WDTIN .ds 1
	.ends

	_TM0CON_SysRegDefine.c .section bank0,addr=15
	_TM0CON .ds 1
	.ends

	_TM0IN_SysRegDefine.c .section bank0,addr=16
	_TM0IN .ds 1
	.ends

	_TM0CNT_SysRegDefine.c .section bank0,addr=17
	_TM0CNT .ds 1
	.ends

	_PAGECTL_SysRegDefine.c .section bank0,addr=20
	_PAGECTL .ds 1
	.ends

	_MCK_SysRegDefine.c .section bank0,addr=22
	_MCK .ds 1
	.ends

	_TM2CON_SysRegDefine.c .section bank0,addr=23
	_TM2CON .ds 1
	.ends

	_TM2IN_SysRegDefine.c .section bank0,addr=24
	_TM2IN .ds 1
	.ends

	_TM2CNT_SysRegDefine.c .section bank0,addr=25
	_TM2CNT .ds 1
	.ends

	_TM2R_SysRegDefine.c .section bank0,addr=26
	_TM2R .ds 1
	.ends

	_TM3CON_SysRegDefine.c .section bank0,addr=27
	_TM3CON .ds 1
	.ends

	_TM3IN_SysRegDefine.c .section bank0,addr=28
	_TM3IN .ds 1
	.ends

	_TM3CNT_SysRegDefine.c .section bank0,addr=29
	_TM3CNT .ds 1
	.ends

	_TM3R_SysRegDefine.c .section bank0,addr=30
	_TM3R .ds 1
	.ends

	_TM3INH_SysRegDefine.c .section bank0,addr=31
	_TM3INH .ds 1
	.ends

	_PT1_SysRegDefine.c .section bank0,addr=32
	_PT1 .ds 1
	.ends

	_PT1EN_SysRegDefine.c .section bank0,addr=33
	_PT1EN .ds 1
	.ends

	_PT1PU_SysRegDefine.c .section bank0,addr=34
	_PT1PU .ds 1
	.ends

	_PT1CON_SysRegDefine.c .section bank0,addr=35
	_PT1CON .ds 1
	.ends

	_TM2INH_SysRegDefine.c .section bank0,addr=36
	_TM2INH .ds 1
	.ends

	_TM2CNTH_SysRegDefine.c .section bank0,addr=37
	_TM2CNTH .ds 1
	.ends

	_TM2RH_SysRegDefine.c .section bank0,addr=38
	_TM2RH .ds 1
	.ends

	_TM3CNTH_SysRegDefine.c .section bank0,addr=39
	_TM3CNTH .ds 1
	.ends

	_PT3_SysRegDefine.c .section bank0,addr=40
	_PT3 .ds 1
	.ends

	_PT3EN_SysRegDefine.c .section bank0,addr=41
	_PT3EN .ds 1
	.ends

	_PT3PU_SysRegDefine.c .section bank0,addr=42
	_PT3PU .ds 1
	.ends

	_PT3CON_SysRegDefine.c .section bank0,addr=43
	_PT3CON .ds 1
	.ends

	_TM3RH_SysRegDefine.c .section bank0,addr=44
	_TM3RH .ds 1
	.ends

	_TM3CON2_SysRegDefine.c .section bank0,addr=45
	_TM3CON2 .ds 1
	.ends

	_CONFIG1_SysRegDefine.c .section bank0,addr=46
	_CONFIG1 .ds 1
	.ends

	_CONFIG2_SysRegDefine.c .section bank0,addr=47
	_CONFIG2 .ds 1
	.ends

	_PT5_SysRegDefine.c .section bank0,addr=48
	_PT5 .ds 1
	.ends

	_PT5EN_SysRegDefine.c .section bank0,addr=49
	_PT5EN .ds 1
	.ends

	_PT5PU_SysRegDefine.c .section bank0,addr=50
	_PT5PU .ds 1
	.ends

	_PT5CON_SysRegDefine.c .section bank0,addr=51
	_PT5CON .ds 1
	.ends

	_SRADCON0_SysRegDefine.c .section bank0,addr=52
	_SRADCON0 .ds 1
	.ends

	_SRADCON1_SysRegDefine.c .section bank0,addr=53
	_SRADCON1 .ds 1
	.ends

	_SRADCON2_SysRegDefine.c .section bank0,addr=54
	_SRADCON2 .ds 1
	.ends

	_SRADL_SysRegDefine.c .section bank0,addr=55
	_SRADL .ds 1
	.ends

	_SRADH_SysRegDefine.c .section bank0,addr=56
	_SRADH .ds 1
	.ends

	_SROFTL_SysRegDefine.c .section bank0,addr=57
	_SROFTL .ds 1
	.ends

	_SROFTH_SysRegDefine.c .section bank0,addr=58
	_SROFTH .ds 1
	.ends

	_INTF2_SysRegDefine.c .section bank0,addr=60
	_INTF2 .ds 1
	.ends

	_INTE2_SysRegDefine.c .section bank0,addr=61
	_INTE2 .ds 1
	.ends

	_INTCFG_SysRegDefine.c .section bank0,addr=64
	_INTCFG .ds 1
	.ends

	_PT1CON1_SysRegDefine.c .section bank0,addr=65
	_PT1CON1 .ds 1
	.ends

	_PT5CON1_SysRegDefine.c .section bank0,addr=66
	_PT5CON1 .ds 1
	.ends

	_TM3CON3_SysRegDefine.c .section bank0,addr=69
	_TM3CON3 .ds 1
	.ends

	_WWDTCR_SysRegDefine.c .section bank0,addr=71
	_WWDTCR .ds 1
	.ends

	_WWDTWR_SysRegDefine.c .section bank0,addr=72
	_WWDTWR .ds 1
	.ends

	_UR0_CR1_SysRegDefine.c .section bank0,addr=80
	_UR0_CR1 .ds 1
	.ends

	_UR0_BRR0_SysRegDefine.c .section bank0,addr=81
	_UR0_BRR0 .ds 1
	.ends

	_UR0_BRR1_SysRegDefine.c .section bank0,addr=82
	_UR0_BRR1 .ds 1
	.ends

	_UR0_TX_REG_SysRegDefine.c .section bank0,addr=83
	_UR0_TX_REG .ds 1
	.ends

	_UR0_RX_REG_SysRegDefine.c .section bank0,addr=84
	_UR0_RX_REG .ds 1
	.ends

	_UR0_ST_SysRegDefine.c .section bank0,addr=85
	_UR0_ST .ds 1
	.ends

	_UR0_INTF_SysRegDefine.c .section bank0,addr=86
	_UR0_INTF .ds 1
	.ends

	_UR0_INTE_SysRegDefine.c .section bank0,addr=87
	_UR0_INTE .ds 1
	.ends

	_I2CCON_SysRegDefine.c .section bank0,addr=89
	_I2CCON .ds 1
	.ends

	_I2CCON1_SysRegDefine.c .section bank0,addr=90
	_I2CCON1 .ds 1
	.ends

	_I2CDAT_SysRegDefine.c .section bank0,addr=91
	_I2CDAT .ds 1
	.ends

	_I2CADR_SysRegDefine.c .section bank0,addr=92
	_I2CADR .ds 1
	.ends

	_I2C_INTF_SysRegDefine.c .section bank0,addr=93
	_I2C_INTF .ds 1
	.ends

	_I2C_INTE_SysRegDefine.c .section bank0,addr=94
	_I2C_INTE .ds 1
	.ends

	_ISPCON1_SysRegDefine.c .section bank0,addr=96
	_ISPCON1 .ds 1
	.ends

	_WRPRT_SysRegDefine.c .section bank0,addr=99
	_WRPRT .ds 1
	.ends

	_TM4CON_SysRegDefine.c .section bank0,addr=100
	_TM4CON .ds 1
	.ends

	_TM4IN_SysRegDefine.c .section bank0,addr=101
	_TM4IN .ds 1
	.ends

	_TM4CNT_SysRegDefine.c .section bank0,addr=102
	_TM4CNT .ds 1
	.ends

	_TM4R_SysRegDefine.c .section bank0,addr=103
	_TM4R .ds 1
	.ends

	_TM4INH_SysRegDefine.c .section bank0,addr=104
	_TM4INH .ds 1
	.ends

	_TM4CNTH_SysRegDefine.c .section bank0,addr=105
	_TM4CNTH .ds 1
	.ends

	_TM4RH_SysRegDefine.c .section bank0,addr=106
	_TM4RH .ds 1
	.ends

	_LEDADR_SysRegDefine.c .section bank0,addr=110
	_LEDADR .ds 1
	.ends

	_LEDDAT_SysRegDefine.c .section bank0,addr=111
	_LEDDAT .ds 1
	.ends

	_LEDDUTY_SysRegDefine.c .section bank0,addr=112
	_LEDDUTY .ds 1
	.ends

	_LEDCOM_SysRegDefine.c .section bank0,addr=113
	_LEDCOM .ds 1
	.ends

	_LEDCON_SysRegDefine.c .section bank0,addr=114
	_LEDCON .ds 1
	.ends

	_LEDCON1_SysRegDefine.c .section bank0,addr=115
	_LEDCON1 .ds 1
	.ends

	_CHPCON_SysRegDefine.c .section bank0,addr=116
	_CHPCON .ds 1
	.ends

	_TBLPEN_SysRegDefine.c .section bank0,addr=119
	_TBLPEN .ds 1
	.ends

	_LVDCON_SysRegDefine.c .section bank0,addr=120
	_LVDCON .ds 1
	.ends

	_MCK1_SysRegDefine.c .section bank0,addr=121
	_MCK1 .ds 1
	.ends

	_PT5_BIGDRV_SysRegDefine.c .section bank0,addr=122
	_PT5_BIGDRV .ds 1
	.ends

	_CONFLASH_SysRegDefine.c .section bank0,addr=124
	_CONFLASH .ds 1
	.ends

	_Z_SysRegDefine.c .section bank0,addr=4,bitfield=0,uninit
	_Z .ds 1
	.ends

	_C_SysRegDefine.c .section bank0,addr=4,bitfield=1,uninit
	_C .ds 1
	.ends

	_DC_SysRegDefine.c .section bank0,addr=4,bitfield=2,uninit
	_DC .ds 1
	.ends

	_TO_SysRegDefine.c .section bank0,addr=4,bitfield=3,uninit
	_TO .ds 1
	.ends

	_PD_SysRegDefine.c .section bank0,addr=4,bitfield=4,uninit
	_PD .ds 1
	.ends

	_E0IF_SysRegDefine.c .section bank0,addr=6,bitfield=0,uninit
	_E0IF .ds 1
	.ends

	_E1IF_SysRegDefine.c .section bank0,addr=6,bitfield=1,uninit
	_E1IF .ds 1
	.ends

	_SRADIF_SysRegDefine.c .section bank0,addr=6,bitfield=3,uninit
	_SRADIF .ds 1
	.ends

	_TM0IF_SysRegDefine.c .section bank0,addr=6,bitfield=4,uninit
	_TM0IF .ds 1
	.ends

	_TM2IF_SysRegDefine.c .section bank0,addr=6,bitfield=6,uninit
	_TM2IF .ds 1
	.ends

	_E0IE_SysRegDefine.c .section bank0,addr=7,bitfield=0,uninit
	_E0IE .ds 1
	.ends

	_E1IE_SysRegDefine.c .section bank0,addr=7,bitfield=1,uninit
	_E1IE .ds 1
	.ends

	_SRADIE_SysRegDefine.c .section bank0,addr=7,bitfield=3,uninit
	_SRADIE .ds 1
	.ends

	_TM0IE_SysRegDefine.c .section bank0,addr=7,bitfield=4,uninit
	_TM0IE .ds 1
	.ends

	_TM2IE_SysRegDefine.c .section bank0,addr=7,bitfield=6,uninit
	_TM2IE .ds 1
	.ends

	_GIE_SysRegDefine.c .section bank0,addr=7,bitfield=7,uninit
	_GIE .ds 1
	.ends

	_PAGE_0_SysRegDefine.c .section bank0,addr=8,bitfield=0,uninit
	_PAGE_0 .ds 1
	.ends

	_IRP0_SysRegDefine.c .section bank0,addr=8,bitfield=7,uninit
	_IRP0 .ds 1
	.ends

	_WWDTF_SysRegDefine.c .section bank0,addr=9,bitfield=0,uninit
	_WWDTF .ds 1
	.ends

	_ILOPF_SysRegDefine.c .section bank0,addr=9,bitfield=1,uninit
	_ILOPF .ds 1
	.ends

	_EMCF_SysRegDefine.c .section bank0,addr=9,bitfield=2,uninit
	_EMCF .ds 1
	.ends

	_EADR_8_SysRegDefine.c .section bank0,addr=10,bitfield=0,uninit
	_EADR_8 .ds 1
	.ends

	_EADR_9_SysRegDefine.c .section bank0,addr=10,bitfield=1,uninit
	_EADR_9 .ds 1
	.ends

	_EADR_10_SysRegDefine.c .section bank0,addr=10,bitfield=2,uninit
	_EADR_10 .ds 1
	.ends

	_EADR_11_SysRegDefine.c .section bank0,addr=10,bitfield=3,uninit
	_EADR_11 .ds 1
	.ends

	_EADR_12_SysRegDefine.c .section bank0,addr=10,bitfield=4,uninit
	_EADR_12 .ds 1
	.ends

	_EADR_13_SysRegDefine.c .section bank0,addr=10,bitfield=5,uninit
	_EADR_13 .ds 1
	.ends

	_EADR_14_SysRegDefine.c .section bank0,addr=10,bitfield=6,uninit
	_EADR_14 .ds 1
	.ends

	_EADR_15_SysRegDefine.c .section bank0,addr=10,bitfield=7,uninit
	_EADR_15 .ds 1
	.ends

	_EADR_0_SysRegDefine.c .section bank0,addr=11,bitfield=0,uninit
	_EADR_0 .ds 1
	.ends

	_EADR_1_SysRegDefine.c .section bank0,addr=11,bitfield=1,uninit
	_EADR_1 .ds 1
	.ends

	_EADR_2_SysRegDefine.c .section bank0,addr=11,bitfield=2,uninit
	_EADR_2 .ds 1
	.ends

	_EADR_3_SysRegDefine.c .section bank0,addr=11,bitfield=3,uninit
	_EADR_3 .ds 1
	.ends

	_EADR_4_SysRegDefine.c .section bank0,addr=11,bitfield=4,uninit
	_EADR_4 .ds 1
	.ends

	_EADR_5_SysRegDefine.c .section bank0,addr=11,bitfield=5,uninit
	_EADR_5 .ds 1
	.ends

	_EADR_6_SysRegDefine.c .section bank0,addr=11,bitfield=6,uninit
	_EADR_6 .ds 1
	.ends

	_EADR_7_SysRegDefine.c .section bank0,addr=11,bitfield=7,uninit
	_EADR_7 .ds 1
	.ends

	_EDATH_0_SysRegDefine.c .section bank0,addr=12,bitfield=0,uninit
	_EDATH_0 .ds 1
	.ends

	_EDATH_1_SysRegDefine.c .section bank0,addr=12,bitfield=1,uninit
	_EDATH_1 .ds 1
	.ends

	_EDATH_2_SysRegDefine.c .section bank0,addr=12,bitfield=2,uninit
	_EDATH_2 .ds 1
	.ends

	_EDATH_3_SysRegDefine.c .section bank0,addr=12,bitfield=3,uninit
	_EDATH_3 .ds 1
	.ends

	_EDATH_4_SysRegDefine.c .section bank0,addr=12,bitfield=4,uninit
	_EDATH_4 .ds 1
	.ends

	_EDATH_5_SysRegDefine.c .section bank0,addr=12,bitfield=5,uninit
	_EDATH_5 .ds 1
	.ends

	_EDATH_6_SysRegDefine.c .section bank0,addr=12,bitfield=6,uninit
	_EDATH_6 .ds 1
	.ends

	_EDATH_7_SysRegDefine.c .section bank0,addr=12,bitfield=7,uninit
	_EDATH_7 .ds 1
	.ends

	_WTS_0_SysRegDefine.c .section bank0,addr=13,bitfield=0,uninit
	_WTS_0 .ds 1
	.ends

	_WTS_1_SysRegDefine.c .section bank0,addr=13,bitfield=1,uninit
	_WTS_1 .ds 1
	.ends

	_WTS_2_SysRegDefine.c .section bank0,addr=13,bitfield=2,uninit
	_WTS_2 .ds 1
	.ends

	_WDTEN_SysRegDefine.c .section bank0,addr=13,bitfield=7,uninit
	_WDTEN .ds 1
	.ends

	_WDTIN_0_SysRegDefine.c .section bank0,addr=14,bitfield=0,uninit
	_WDTIN_0 .ds 1
	.ends

	_WDTIN_1_SysRegDefine.c .section bank0,addr=14,bitfield=1,uninit
	_WDTIN_1 .ds 1
	.ends

	_WDTIN_2_SysRegDefine.c .section bank0,addr=14,bitfield=2,uninit
	_WDTIN_2 .ds 1
	.ends

	_WDTIN_3_SysRegDefine.c .section bank0,addr=14,bitfield=3,uninit
	_WDTIN_3 .ds 1
	.ends

	_WDTIN_4_SysRegDefine.c .section bank0,addr=14,bitfield=4,uninit
	_WDTIN_4 .ds 1
	.ends

	_WDTIN_5_SysRegDefine.c .section bank0,addr=14,bitfield=5,uninit
	_WDTIN_5 .ds 1
	.ends

	_WDTIN_6_SysRegDefine.c .section bank0,addr=14,bitfield=6,uninit
	_WDTIN_6 .ds 1
	.ends

	_WDTIN_7_SysRegDefine.c .section bank0,addr=14,bitfield=7,uninit
	_WDTIN_7 .ds 1
	.ends

	_T0SEL_0_SysRegDefine.c .section bank0,addr=15,bitfield=0,uninit
	_T0SEL_0 .ds 1
	.ends

	_T0SEL_1_SysRegDefine.c .section bank0,addr=15,bitfield=1,uninit
	_T0SEL_1 .ds 1
	.ends

	_T0RSTB_SysRegDefine.c .section bank0,addr=15,bitfield=2,uninit
	_T0RSTB .ds 1
	.ends

	_T0RATE_0_SysRegDefine.c .section bank0,addr=15,bitfield=4,uninit
	_T0RATE_0 .ds 1
	.ends

	_T0RATE_1_SysRegDefine.c .section bank0,addr=15,bitfield=5,uninit
	_T0RATE_1 .ds 1
	.ends

	_T0RATE_2_SysRegDefine.c .section bank0,addr=15,bitfield=6,uninit
	_T0RATE_2 .ds 1
	.ends

	_T0EN_SysRegDefine.c .section bank0,addr=15,bitfield=7,uninit
	_T0EN .ds 1
	.ends

	_TM0IN_0_SysRegDefine.c .section bank0,addr=16,bitfield=0,uninit
	_TM0IN_0 .ds 1
	.ends

	_TM0IN_1_SysRegDefine.c .section bank0,addr=16,bitfield=1,uninit
	_TM0IN_1 .ds 1
	.ends

	_TM0IN_2_SysRegDefine.c .section bank0,addr=16,bitfield=2,uninit
	_TM0IN_2 .ds 1
	.ends

	_TM0IN_3_SysRegDefine.c .section bank0,addr=16,bitfield=3,uninit
	_TM0IN_3 .ds 1
	.ends

	_TM0IN_4_SysRegDefine.c .section bank0,addr=16,bitfield=4,uninit
	_TM0IN_4 .ds 1
	.ends

	_TM0IN_5_SysRegDefine.c .section bank0,addr=16,bitfield=5,uninit
	_TM0IN_5 .ds 1
	.ends

	_TM0IN_6_SysRegDefine.c .section bank0,addr=16,bitfield=6,uninit
	_TM0IN_6 .ds 1
	.ends

	_TM0IN_7_SysRegDefine.c .section bank0,addr=16,bitfield=7,uninit
	_TM0IN_7 .ds 1
	.ends

	_TM0CNT_0_SysRegDefine.c .section bank0,addr=17,bitfield=0,uninit
	_TM0CNT_0 .ds 1
	.ends

	_TM0CNT_1_SysRegDefine.c .section bank0,addr=17,bitfield=1,uninit
	_TM0CNT_1 .ds 1
	.ends

	_TM0CNT_2_SysRegDefine.c .section bank0,addr=17,bitfield=2,uninit
	_TM0CNT_2 .ds 1
	.ends

	_TM0CNT_3_SysRegDefine.c .section bank0,addr=17,bitfield=3,uninit
	_TM0CNT_3 .ds 1
	.ends

	_TM0CNT_4_SysRegDefine.c .section bank0,addr=17,bitfield=4,uninit
	_TM0CNT_4 .ds 1
	.ends

	_TM0CNT_5_SysRegDefine.c .section bank0,addr=17,bitfield=5,uninit
	_TM0CNT_5 .ds 1
	.ends

	_TM0CNT_6_SysRegDefine.c .section bank0,addr=17,bitfield=6,uninit
	_TM0CNT_6 .ds 1
	.ends

	_TM0CNT_7_SysRegDefine.c .section bank0,addr=17,bitfield=7,uninit
	_TM0CNT_7 .ds 1
	.ends

	_PAGE2_SysRegDefine.c .section bank0,addr=20,bitfield=0,uninit
	_PAGE2 .ds 1
	.ends

	_CST_WDT_SysRegDefine.c .section bank0,addr=22,bitfield=5,uninit
	_CST_WDT .ds 1
	.ends

	_PWM2OUT_SysRegDefine.c .section bank0,addr=23,bitfield=0,uninit
	_PWM2OUT .ds 1
	.ends

	_T2OUT_SysRegDefine.c .section bank0,addr=23,bitfield=1,uninit
	_T2OUT .ds 1
	.ends

	_T2RSTB_SysRegDefine.c .section bank0,addr=23,bitfield=2,uninit
	_T2RSTB .ds 1
	.ends

	_T2CKS_SysRegDefine.c .section bank0,addr=23,bitfield=3,uninit
	_T2CKS .ds 1
	.ends

	_T2RATE_0_SysRegDefine.c .section bank0,addr=23,bitfield=4,uninit
	_T2RATE_0 .ds 1
	.ends

	_T2RATE_1_SysRegDefine.c .section bank0,addr=23,bitfield=5,uninit
	_T2RATE_1 .ds 1
	.ends

	_T2RATE_2_SysRegDefine.c .section bank0,addr=23,bitfield=6,uninit
	_T2RATE_2 .ds 1
	.ends

	_T2EN_SysRegDefine.c .section bank0,addr=23,bitfield=7,uninit
	_T2EN .ds 1
	.ends

	_TM2IN_0_SysRegDefine.c .section bank0,addr=24,bitfield=0,uninit
	_TM2IN_0 .ds 1
	.ends

	_TM2IN_1_SysRegDefine.c .section bank0,addr=24,bitfield=1,uninit
	_TM2IN_1 .ds 1
	.ends

	_TM2IN_2_SysRegDefine.c .section bank0,addr=24,bitfield=2,uninit
	_TM2IN_2 .ds 1
	.ends

	_TM2IN_3_SysRegDefine.c .section bank0,addr=24,bitfield=3,uninit
	_TM2IN_3 .ds 1
	.ends

	_TM2IN_4_SysRegDefine.c .section bank0,addr=24,bitfield=4,uninit
	_TM2IN_4 .ds 1
	.ends

	_TM2IN_5_SysRegDefine.c .section bank0,addr=24,bitfield=5,uninit
	_TM2IN_5 .ds 1
	.ends

	_TM2IN_6_SysRegDefine.c .section bank0,addr=24,bitfield=6,uninit
	_TM2IN_6 .ds 1
	.ends

	_TM2IN_7_SysRegDefine.c .section bank0,addr=24,bitfield=7,uninit
	_TM2IN_7 .ds 1
	.ends

	_TM2CNT_0_SysRegDefine.c .section bank0,addr=25,bitfield=0,uninit
	_TM2CNT_0 .ds 1
	.ends

	_TM2CNT_1_SysRegDefine.c .section bank0,addr=25,bitfield=1,uninit
	_TM2CNT_1 .ds 1
	.ends

	_TM2CNT_2_SysRegDefine.c .section bank0,addr=25,bitfield=2,uninit
	_TM2CNT_2 .ds 1
	.ends

	_TM2CNT_3_SysRegDefine.c .section bank0,addr=25,bitfield=3,uninit
	_TM2CNT_3 .ds 1
	.ends

	_TM2CNT_4_SysRegDefine.c .section bank0,addr=25,bitfield=4,uninit
	_TM2CNT_4 .ds 1
	.ends

	_TM2CNT_5_SysRegDefine.c .section bank0,addr=25,bitfield=5,uninit
	_TM2CNT_5 .ds 1
	.ends

	_TM2CNT_6_SysRegDefine.c .section bank0,addr=25,bitfield=6,uninit
	_TM2CNT_6 .ds 1
	.ends

	_TM2CNT_7_SysRegDefine.c .section bank0,addr=25,bitfield=7,uninit
	_TM2CNT_7 .ds 1
	.ends

	_TM2R_0_SysRegDefine.c .section bank0,addr=26,bitfield=0,uninit
	_TM2R_0 .ds 1
	.ends

	_TM2R_1_SysRegDefine.c .section bank0,addr=26,bitfield=1,uninit
	_TM2R_1 .ds 1
	.ends

	_TM2R_2_SysRegDefine.c .section bank0,addr=26,bitfield=2,uninit
	_TM2R_2 .ds 1
	.ends

	_TM2R_3_SysRegDefine.c .section bank0,addr=26,bitfield=3,uninit
	_TM2R_3 .ds 1
	.ends

	_TM2R_4_SysRegDefine.c .section bank0,addr=26,bitfield=4,uninit
	_TM2R_4 .ds 1
	.ends

	_TM2R_5_SysRegDefine.c .section bank0,addr=26,bitfield=5,uninit
	_TM2R_5 .ds 1
	.ends

	_TM2R_6_SysRegDefine.c .section bank0,addr=26,bitfield=6,uninit
	_TM2R_6 .ds 1
	.ends

	_TM2R_7_SysRegDefine.c .section bank0,addr=26,bitfield=7,uninit
	_TM2R_7 .ds 1
	.ends

	_PWM3OUT_SysRegDefine.c .section bank0,addr=27,bitfield=0,uninit
	_PWM3OUT .ds 1
	.ends

	_T3OUT_SysRegDefine.c .section bank0,addr=27,bitfield=1,uninit
	_T3OUT .ds 1
	.ends

	_T3RSTB_SysRegDefine.c .section bank0,addr=27,bitfield=2,uninit
	_T3RSTB .ds 1
	.ends

	_T3CKS_SysRegDefine.c .section bank0,addr=27,bitfield=3,uninit
	_T3CKS .ds 1
	.ends

	_T3RATE_0_SysRegDefine.c .section bank0,addr=27,bitfield=4,uninit
	_T3RATE_0 .ds 1
	.ends

	_T3RATE_1_SysRegDefine.c .section bank0,addr=27,bitfield=5,uninit
	_T3RATE_1 .ds 1
	.ends

	_T3RATE_2_SysRegDefine.c .section bank0,addr=27,bitfield=6,uninit
	_T3RATE_2 .ds 1
	.ends

	_T3EN_SysRegDefine.c .section bank0,addr=27,bitfield=7,uninit
	_T3EN .ds 1
	.ends

	_TM3IN_0_SysRegDefine.c .section bank0,addr=28,bitfield=0,uninit
	_TM3IN_0 .ds 1
	.ends

	_TM3IN_1_SysRegDefine.c .section bank0,addr=28,bitfield=1,uninit
	_TM3IN_1 .ds 1
	.ends

	_TM3IN_2_SysRegDefine.c .section bank0,addr=28,bitfield=2,uninit
	_TM3IN_2 .ds 1
	.ends

	_TM3IN_3_SysRegDefine.c .section bank0,addr=28,bitfield=3,uninit
	_TM3IN_3 .ds 1
	.ends

	_TM3IN_4_SysRegDefine.c .section bank0,addr=28,bitfield=4,uninit
	_TM3IN_4 .ds 1
	.ends

	_TM3IN_5_SysRegDefine.c .section bank0,addr=28,bitfield=5,uninit
	_TM3IN_5 .ds 1
	.ends

	_TM3IN_6_SysRegDefine.c .section bank0,addr=28,bitfield=6,uninit
	_TM3IN_6 .ds 1
	.ends

	_TM3IN_7_SysRegDefine.c .section bank0,addr=28,bitfield=7,uninit
	_TM3IN_7 .ds 1
	.ends

	_TM3CNT_0_SysRegDefine.c .section bank0,addr=29,bitfield=0,uninit
	_TM3CNT_0 .ds 1
	.ends

	_TM3CNT_1_SysRegDefine.c .section bank0,addr=29,bitfield=1,uninit
	_TM3CNT_1 .ds 1
	.ends

	_TM3CNT_2_SysRegDefine.c .section bank0,addr=29,bitfield=2,uninit
	_TM3CNT_2 .ds 1
	.ends

	_TM3CNT_3_SysRegDefine.c .section bank0,addr=29,bitfield=3,uninit
	_TM3CNT_3 .ds 1
	.ends

	_TM3CNT_4_SysRegDefine.c .section bank0,addr=29,bitfield=4,uninit
	_TM3CNT_4 .ds 1
	.ends

	_TM3CNT_5_SysRegDefine.c .section bank0,addr=29,bitfield=5,uninit
	_TM3CNT_5 .ds 1
	.ends

	_TM3CNT_6_SysRegDefine.c .section bank0,addr=29,bitfield=6,uninit
	_TM3CNT_6 .ds 1
	.ends

	_TM3CNT_7_SysRegDefine.c .section bank0,addr=29,bitfield=7,uninit
	_TM3CNT_7 .ds 1
	.ends

	_TM3R_0_SysRegDefine.c .section bank0,addr=30,bitfield=0,uninit
	_TM3R_0 .ds 1
	.ends

	_TM3R_1_SysRegDefine.c .section bank0,addr=30,bitfield=1,uninit
	_TM3R_1 .ds 1
	.ends

	_TM3R_2_SysRegDefine.c .section bank0,addr=30,bitfield=2,uninit
	_TM3R_2 .ds 1
	.ends

	_TM3R_3_SysRegDefine.c .section bank0,addr=30,bitfield=3,uninit
	_TM3R_3 .ds 1
	.ends

	_TM3R_4_SysRegDefine.c .section bank0,addr=30,bitfield=4,uninit
	_TM3R_4 .ds 1
	.ends

	_TM3R_5_SysRegDefine.c .section bank0,addr=30,bitfield=5,uninit
	_TM3R_5 .ds 1
	.ends

	_TM3R_6_SysRegDefine.c .section bank0,addr=30,bitfield=6,uninit
	_TM3R_6 .ds 1
	.ends

	_TM3R_7_SysRegDefine.c .section bank0,addr=30,bitfield=7,uninit
	_TM3R_7 .ds 1
	.ends

	_TM3INH_8_SysRegDefine.c .section bank0,addr=31,bitfield=0,uninit
	_TM3INH_8 .ds 1
	.ends

	_TM3INH_9_SysRegDefine.c .section bank0,addr=31,bitfield=1,uninit
	_TM3INH_9 .ds 1
	.ends

	_TM3INH_10_SysRegDefine.c .section bank0,addr=31,bitfield=2,uninit
	_TM3INH_10 .ds 1
	.ends

	_TM3INH_11_SysRegDefine.c .section bank0,addr=31,bitfield=3,uninit
	_TM3INH_11 .ds 1
	.ends

	_PT1_0_SysRegDefine.c .section bank0,addr=32,bitfield=0,uninit
	_PT1_0 .ds 1
	.ends

	_PT1_3_SysRegDefine.c .section bank0,addr=32,bitfield=3,uninit
	_PT1_3 .ds 1
	.ends

	_PT1_4_SysRegDefine.c .section bank0,addr=32,bitfield=4,uninit
	_PT1_4 .ds 1
	.ends

	_PT1_5_SysRegDefine.c .section bank0,addr=32,bitfield=5,uninit
	_PT1_5 .ds 1
	.ends

	_PT1EN_0_SysRegDefine.c .section bank0,addr=33,bitfield=0,uninit
	_PT1EN_0 .ds 1
	.ends

	_PT1EN_3_SysRegDefine.c .section bank0,addr=33,bitfield=3,uninit
	_PT1EN_3 .ds 1
	.ends

	_PT1EN_4_SysRegDefine.c .section bank0,addr=33,bitfield=4,uninit
	_PT1EN_4 .ds 1
	.ends

	_PT1EN_5_SysRegDefine.c .section bank0,addr=33,bitfield=5,uninit
	_PT1EN_5 .ds 1
	.ends

	_PT1PU_0_SysRegDefine.c .section bank0,addr=34,bitfield=0,uninit
	_PT1PU_0 .ds 1
	.ends

	_PT1PU_3_SysRegDefine.c .section bank0,addr=34,bitfield=3,uninit
	_PT1PU_3 .ds 1
	.ends

	_PT1PU_4_SysRegDefine.c .section bank0,addr=34,bitfield=4,uninit
	_PT1PU_4 .ds 1
	.ends

	_PT1PU_5_SysRegDefine.c .section bank0,addr=34,bitfield=5,uninit
	_PT1PU_5 .ds 1
	.ends

	_E0M_0_SysRegDefine.c .section bank0,addr=35,bitfield=0,uninit
	_E0M_0 .ds 1
	.ends

	_E0M_1_SysRegDefine.c .section bank0,addr=35,bitfield=1,uninit
	_E0M_1 .ds 1
	.ends

	_E1M_SysRegDefine.c .section bank0,addr=35,bitfield=2,uninit
	_E1M .ds 1
	.ends

	_PT1W_0_SysRegDefine.c .section bank0,addr=35,bitfield=3,uninit
	_PT1W_0 .ds 1
	.ends

	_PT1W_1_SysRegDefine.c .section bank0,addr=35,bitfield=4,uninit
	_PT1W_1 .ds 1
	.ends

	_PT1W_2_SysRegDefine.c .section bank0,addr=35,bitfield=5,uninit
	_PT1W_2 .ds 1
	.ends

	_TM2IN_8_SysRegDefine.c .section bank0,addr=36,bitfield=0,uninit
	_TM2IN_8 .ds 1
	.ends

	_TM2IN_9_SysRegDefine.c .section bank0,addr=36,bitfield=1,uninit
	_TM2IN_9 .ds 1
	.ends

	_TM2IN_10_SysRegDefine.c .section bank0,addr=36,bitfield=2,uninit
	_TM2IN_10 .ds 1
	.ends

	_TM2IN_11_SysRegDefine.c .section bank0,addr=36,bitfield=3,uninit
	_TM2IN_11 .ds 1
	.ends

	_TM2CNT_8_SysRegDefine.c .section bank0,addr=37,bitfield=0,uninit
	_TM2CNT_8 .ds 1
	.ends

	_TM2CNT_9_SysRegDefine.c .section bank0,addr=37,bitfield=1,uninit
	_TM2CNT_9 .ds 1
	.ends

	_TM2CNT_10_SysRegDefine.c .section bank0,addr=37,bitfield=2,uninit
	_TM2CNT_10 .ds 1
	.ends

	_TM2CNT_11_SysRegDefine.c .section bank0,addr=37,bitfield=3,uninit
	_TM2CNT_11 .ds 1
	.ends

	_TM2R_8_SysRegDefine.c .section bank0,addr=38,bitfield=0,uninit
	_TM2R_8 .ds 1
	.ends

	_TM2R_9_SysRegDefine.c .section bank0,addr=38,bitfield=1,uninit
	_TM2R_9 .ds 1
	.ends

	_TM2R_10_SysRegDefine.c .section bank0,addr=38,bitfield=2,uninit
	_TM2R_10 .ds 1
	.ends

	_TM2R_11_SysRegDefine.c .section bank0,addr=38,bitfield=3,uninit
	_TM2R_11 .ds 1
	.ends

	_TM3CNT_8_SysRegDefine.c .section bank0,addr=39,bitfield=0,uninit
	_TM3CNT_8 .ds 1
	.ends

	_TM3CNT_9_SysRegDefine.c .section bank0,addr=39,bitfield=1,uninit
	_TM3CNT_9 .ds 1
	.ends

	_TM3CNT_10_SysRegDefine.c .section bank0,addr=39,bitfield=2,uninit
	_TM3CNT_10 .ds 1
	.ends

	_TM3CNT_11_SysRegDefine.c .section bank0,addr=39,bitfield=3,uninit
	_TM3CNT_11 .ds 1
	.ends

	_PT3_0_SysRegDefine.c .section bank0,addr=40,bitfield=0,uninit
	_PT3_0 .ds 1
	.ends

	_PT3_1_SysRegDefine.c .section bank0,addr=40,bitfield=1,uninit
	_PT3_1 .ds 1
	.ends

	_PT3_2_SysRegDefine.c .section bank0,addr=40,bitfield=2,uninit
	_PT3_2 .ds 1
	.ends

	_PT3_3_SysRegDefine.c .section bank0,addr=40,bitfield=3,uninit
	_PT3_3 .ds 1
	.ends

	_PT3_4_SysRegDefine.c .section bank0,addr=40,bitfield=4,uninit
	_PT3_4 .ds 1
	.ends

	_PT3_5_SysRegDefine.c .section bank0,addr=40,bitfield=5,uninit
	_PT3_5 .ds 1
	.ends

	_PT3_6_SysRegDefine.c .section bank0,addr=40,bitfield=6,uninit
	_PT3_6 .ds 1
	.ends

	_PT3EN_0_SysRegDefine.c .section bank0,addr=41,bitfield=0,uninit
	_PT3EN_0 .ds 1
	.ends

	_PT3EN_1_SysRegDefine.c .section bank0,addr=41,bitfield=1,uninit
	_PT3EN_1 .ds 1
	.ends

	_PT3EN_2_SysRegDefine.c .section bank0,addr=41,bitfield=2,uninit
	_PT3EN_2 .ds 1
	.ends

	_PT3EN_3_SysRegDefine.c .section bank0,addr=41,bitfield=3,uninit
	_PT3EN_3 .ds 1
	.ends

	_PT3EN_4_SysRegDefine.c .section bank0,addr=41,bitfield=4,uninit
	_PT3EN_4 .ds 1
	.ends

	_PT3EN_5_SysRegDefine.c .section bank0,addr=41,bitfield=5,uninit
	_PT3EN_5 .ds 1
	.ends

	_PT3EN_6_SysRegDefine.c .section bank0,addr=41,bitfield=6,uninit
	_PT3EN_6 .ds 1
	.ends

	_PT3PU_0_SysRegDefine.c .section bank0,addr=42,bitfield=0,uninit
	_PT3PU_0 .ds 1
	.ends

	_PT3PU_1_SysRegDefine.c .section bank0,addr=42,bitfield=1,uninit
	_PT3PU_1 .ds 1
	.ends

	_PT3PU_2_SysRegDefine.c .section bank0,addr=42,bitfield=2,uninit
	_PT3PU_2 .ds 1
	.ends

	_PT3PU_3_SysRegDefine.c .section bank0,addr=42,bitfield=3,uninit
	_PT3PU_3 .ds 1
	.ends

	_PT3PU_4_SysRegDefine.c .section bank0,addr=42,bitfield=4,uninit
	_PT3PU_4 .ds 1
	.ends

	_PT3PU_5_SysRegDefine.c .section bank0,addr=42,bitfield=5,uninit
	_PT3PU_5 .ds 1
	.ends

	_PT3PU_6_SysRegDefine.c .section bank0,addr=42,bitfield=6,uninit
	_PT3PU_6 .ds 1
	.ends

	_PT3CON_0_SysRegDefine.c .section bank0,addr=43,bitfield=0,uninit
	_PT3CON_0 .ds 1
	.ends

	_PT3CON_1_SysRegDefine.c .section bank0,addr=43,bitfield=1,uninit
	_PT3CON_1 .ds 1
	.ends

	_PT3CON_2_SysRegDefine.c .section bank0,addr=43,bitfield=2,uninit
	_PT3CON_2 .ds 1
	.ends

	_PT3CON_3_SysRegDefine.c .section bank0,addr=43,bitfield=3,uninit
	_PT3CON_3 .ds 1
	.ends

	_PT3CON_4_SysRegDefine.c .section bank0,addr=43,bitfield=4,uninit
	_PT3CON_4 .ds 1
	.ends

	_PT3CON_5_SysRegDefine.c .section bank0,addr=43,bitfield=5,uninit
	_PT3CON_5 .ds 1
	.ends

	_PT3CON_6_SysRegDefine.c .section bank0,addr=43,bitfield=6,uninit
	_PT3CON_6 .ds 1
	.ends

	_TM3R_8_SysRegDefine.c .section bank0,addr=44,bitfield=0,uninit
	_TM3R_8 .ds 1
	.ends

	_TM3R_9_SysRegDefine.c .section bank0,addr=44,bitfield=1,uninit
	_TM3R_9 .ds 1
	.ends

	_TM3R_10_SysRegDefine.c .section bank0,addr=44,bitfield=2,uninit
	_TM3R_10 .ds 1
	.ends

	_TM3R_11_SysRegDefine.c .section bank0,addr=44,bitfield=3,uninit
	_TM3R_11 .ds 1
	.ends

	_P3L_OEN_SysRegDefine.c .section bank0,addr=45,bitfield=0,uninit
	_P3L_OEN .ds 1
	.ends

	_P3H_OEN_SysRegDefine.c .section bank0,addr=45,bitfield=1,uninit
	_P3H_OEN .ds 1
	.ends

	_DT3_EN_SysRegDefine.c .section bank0,addr=45,bitfield=2,uninit
	_DT3_EN .ds 1
	.ends

	_DT3CNT_0_SysRegDefine.c .section bank0,addr=45,bitfield=3,uninit
	_DT3CNT_0 .ds 1
	.ends

	_DT3CNT_1_SysRegDefine.c .section bank0,addr=45,bitfield=4,uninit
	_DT3CNT_1 .ds 1
	.ends

	_DT3CNT_2_SysRegDefine.c .section bank0,addr=45,bitfield=5,uninit
	_DT3CNT_2 .ds 1
	.ends

	_DT3CK_0_SysRegDefine.c .section bank0,addr=45,bitfield=6,uninit
	_DT3CK_0 .ds 1
	.ends

	_DT3CK_1_SysRegDefine.c .section bank0,addr=45,bitfield=7,uninit
	_DT3CK_1 .ds 1
	.ends

	_PWM2PO_SysRegDefine.c .section bank0,addr=46,bitfield=2,uninit
	_PWM2PO .ds 1
	.ends

	_PWM2STALL_SysRegDefine.c .section bank0,addr=46,bitfield=3,uninit
	_PWM2STALL .ds 1
	.ends

	_PWM3STALL_SysRegDefine.c .section bank0,addr=46,bitfield=4,uninit
	_PWM3STALL .ds 1
	.ends

	_PWM4STALL_SysRegDefine.c .section bank0,addr=46,bitfield=5,uninit
	_PWM4STALL .ds 1
	.ends

	_P3LINV_SysRegDefine.c .section bank0,addr=46,bitfield=6,uninit
	_P3LINV .ds 1
	.ends

	_P3HINV_SysRegDefine.c .section bank0,addr=46,bitfield=7,uninit
	_P3HINV .ds 1
	.ends

	_T4RATE_3_SysRegDefine.c .section bank0,addr=47,bitfield=0,uninit
	_T4RATE_3 .ds 1
	.ends

	_T2RATE_3_SysRegDefine.c .section bank0,addr=47,bitfield=1,uninit
	_T2RATE_3 .ds 1
	.ends

	_T3RATE_3_SysRegDefine.c .section bank0,addr=47,bitfield=2,uninit
	_T3RATE_3 .ds 1
	.ends

	_PWMIS_SysRegDefine.c .section bank0,addr=47,bitfield=3,uninit
	_PWMIS .ds 1
	.ends

	_VTHSEL_SysRegDefine.c .section bank0,addr=47,bitfield=7,uninit
	_VTHSEL .ds 1
	.ends

	_PT5_0_SysRegDefine.c .section bank0,addr=48,bitfield=0,uninit
	_PT5_0 .ds 1
	.ends

	_PT5_1_SysRegDefine.c .section bank0,addr=48,bitfield=1,uninit
	_PT5_1 .ds 1
	.ends

	_PT5_2_SysRegDefine.c .section bank0,addr=48,bitfield=2,uninit
	_PT5_2 .ds 1
	.ends

	_PT5_3_SysRegDefine.c .section bank0,addr=48,bitfield=3,uninit
	_PT5_3 .ds 1
	.ends

	_PT5_4_SysRegDefine.c .section bank0,addr=48,bitfield=4,uninit
	_PT5_4 .ds 1
	.ends

	_PT5_5_SysRegDefine.c .section bank0,addr=48,bitfield=5,uninit
	_PT5_5 .ds 1
	.ends

	_PT5_6_SysRegDefine.c .section bank0,addr=48,bitfield=6,uninit
	_PT5_6 .ds 1
	.ends

	_PT5_7_SysRegDefine.c .section bank0,addr=48,bitfield=7,uninit
	_PT5_7 .ds 1
	.ends

	_PT5EN_0_SysRegDefine.c .section bank0,addr=49,bitfield=0,uninit
	_PT5EN_0 .ds 1
	.ends

	_PT5EN_1_SysRegDefine.c .section bank0,addr=49,bitfield=1,uninit
	_PT5EN_1 .ds 1
	.ends

	_PT5EN_2_SysRegDefine.c .section bank0,addr=49,bitfield=2,uninit
	_PT5EN_2 .ds 1
	.ends

	_PT5EN_3_SysRegDefine.c .section bank0,addr=49,bitfield=3,uninit
	_PT5EN_3 .ds 1
	.ends

	_PT5EN_4_SysRegDefine.c .section bank0,addr=49,bitfield=4,uninit
	_PT5EN_4 .ds 1
	.ends

	_PT5EN_5_SysRegDefine.c .section bank0,addr=49,bitfield=5,uninit
	_PT5EN_5 .ds 1
	.ends

	_PT5EN_6_SysRegDefine.c .section bank0,addr=49,bitfield=6,uninit
	_PT5EN_6 .ds 1
	.ends

	_PT5EN_7_SysRegDefine.c .section bank0,addr=49,bitfield=7,uninit
	_PT5EN_7 .ds 1
	.ends

	_PT5PU_0_SysRegDefine.c .section bank0,addr=50,bitfield=0,uninit
	_PT5PU_0 .ds 1
	.ends

	_PT5PU_1_SysRegDefine.c .section bank0,addr=50,bitfield=1,uninit
	_PT5PU_1 .ds 1
	.ends

	_PT5PU_2_SysRegDefine.c .section bank0,addr=50,bitfield=2,uninit
	_PT5PU_2 .ds 1
	.ends

	_PT5PU_3_SysRegDefine.c .section bank0,addr=50,bitfield=3,uninit
	_PT5PU_3 .ds 1
	.ends

	_PT5PU_4_SysRegDefine.c .section bank0,addr=50,bitfield=4,uninit
	_PT5PU_4 .ds 1
	.ends

	_PT5PU_5_SysRegDefine.c .section bank0,addr=50,bitfield=5,uninit
	_PT5PU_5 .ds 1
	.ends

	_PT5PU_6_SysRegDefine.c .section bank0,addr=50,bitfield=6,uninit
	_PT5PU_6 .ds 1
	.ends

	_PT5PU_7_SysRegDefine.c .section bank0,addr=50,bitfield=7,uninit
	_PT5PU_7 .ds 1
	.ends

	_PT5CON_0_SysRegDefine.c .section bank0,addr=51,bitfield=0,uninit
	_PT5CON_0 .ds 1
	.ends

	_PT5CON_1_SysRegDefine.c .section bank0,addr=51,bitfield=1,uninit
	_PT5CON_1 .ds 1
	.ends

	_PT5CON_2_SysRegDefine.c .section bank0,addr=51,bitfield=2,uninit
	_PT5CON_2 .ds 1
	.ends

	_PT5CON_3_SysRegDefine.c .section bank0,addr=51,bitfield=3,uninit
	_PT5CON_3 .ds 1
	.ends

	_PT5CON_4_SysRegDefine.c .section bank0,addr=51,bitfield=4,uninit
	_PT5CON_4 .ds 1
	.ends

	_PT5CON_5_SysRegDefine.c .section bank0,addr=51,bitfield=5,uninit
	_PT5CON_5 .ds 1
	.ends

	_PT5CON_6_SysRegDefine.c .section bank0,addr=51,bitfield=6,uninit
	_PT5CON_6 .ds 1
	.ends

	_PT5CON_7_SysRegDefine.c .section bank0,addr=51,bitfield=7,uninit
	_PT5CON_7 .ds 1
	.ends

	_SRADCKS_0_SysRegDefine.c .section bank0,addr=52,bitfield=0,uninit
	_SRADCKS_0 .ds 1
	.ends

	_SRADCKS_1_SysRegDefine.c .section bank0,addr=52,bitfield=1,uninit
	_SRADCKS_1 .ds 1
	.ends

	_SRADACKS_0_SysRegDefine.c .section bank0,addr=52,bitfield=4,uninit
	_SRADACKS_0 .ds 1
	.ends

	_SRADACKS_1_SysRegDefine.c .section bank0,addr=52,bitfield=5,uninit
	_SRADACKS_1 .ds 1
	.ends

	_SARVCMSEL_SysRegDefine.c .section bank0,addr=52,bitfield=6,uninit
	_SARVCMSEL .ds 1
	.ends

	_VREFS_0_SysRegDefine.c .section bank0,addr=53,bitfield=0,uninit
	_VREFS_0 .ds 1
	.ends

	_VREFS_1_SysRegDefine.c .section bank0,addr=53,bitfield=1,uninit
	_VREFS_1 .ds 1
	.ends

	_OFFEX_SysRegDefine.c .section bank0,addr=53,bitfield=2,uninit
	_OFFEX .ds 1
	.ends

	_ENOV_SysRegDefine.c .section bank0,addr=53,bitfield=3,uninit
	_ENOV .ds 1
	.ends

	_CALIF_SysRegDefine.c .section bank0,addr=53,bitfield=4,uninit
	_CALIF .ds 1
	.ends

	_OFTEN_SysRegDefine.c .section bank0,addr=53,bitfield=5,uninit
	_OFTEN .ds 1
	.ends

	_SRADS_SysRegDefine.c .section bank0,addr=53,bitfield=6,uninit
	_SRADS .ds 1
	.ends

	_SRADEN_SysRegDefine.c .section bank0,addr=53,bitfield=7,uninit
	_SRADEN .ds 1
	.ends

	_SAR_DIFFEN_SysRegDefine.c .section bank0,addr=54,bitfield=0,uninit
	_SAR_DIFFEN .ds 1
	.ends

	_CHS_0_SysRegDefine.c .section bank0,addr=54,bitfield=4,uninit
	_CHS_0 .ds 1
	.ends

	_CHS_1_SysRegDefine.c .section bank0,addr=54,bitfield=5,uninit
	_CHS_1 .ds 1
	.ends

	_CHS_2_SysRegDefine.c .section bank0,addr=54,bitfield=6,uninit
	_CHS_2 .ds 1
	.ends

	_CHS_3_SysRegDefine.c .section bank0,addr=54,bitfield=7,uninit
	_CHS_3 .ds 1
	.ends

	_SRAD_0_SysRegDefine.c .section bank0,addr=55,bitfield=0,uninit
	_SRAD_0 .ds 1
	.ends

	_SRAD_1_SysRegDefine.c .section bank0,addr=55,bitfield=1,uninit
	_SRAD_1 .ds 1
	.ends

	_SRAD_2_SysRegDefine.c .section bank0,addr=55,bitfield=2,uninit
	_SRAD_2 .ds 1
	.ends

	_SRAD_3_SysRegDefine.c .section bank0,addr=55,bitfield=3,uninit
	_SRAD_3 .ds 1
	.ends

	_SRAD_4_SysRegDefine.c .section bank0,addr=55,bitfield=4,uninit
	_SRAD_4 .ds 1
	.ends

	_SRAD_5_SysRegDefine.c .section bank0,addr=55,bitfield=5,uninit
	_SRAD_5 .ds 1
	.ends

	_SRAD_6_SysRegDefine.c .section bank0,addr=55,bitfield=6,uninit
	_SRAD_6 .ds 1
	.ends

	_SRAD_7_SysRegDefine.c .section bank0,addr=55,bitfield=7,uninit
	_SRAD_7 .ds 1
	.ends

	_SRAD_8_SysRegDefine.c .section bank0,addr=56,bitfield=0,uninit
	_SRAD_8 .ds 1
	.ends

	_SRAD_9_SysRegDefine.c .section bank0,addr=56,bitfield=1,uninit
	_SRAD_9 .ds 1
	.ends

	_SRAD_10_SysRegDefine.c .section bank0,addr=56,bitfield=2,uninit
	_SRAD_10 .ds 1
	.ends

	_SRAD_11_SysRegDefine.c .section bank0,addr=56,bitfield=3,uninit
	_SRAD_11 .ds 1
	.ends

	_SROFT_0_SysRegDefine.c .section bank0,addr=57,bitfield=0,uninit
	_SROFT_0 .ds 1
	.ends

	_SROFT_1_SysRegDefine.c .section bank0,addr=57,bitfield=1,uninit
	_SROFT_1 .ds 1
	.ends

	_SROFT_2_SysRegDefine.c .section bank0,addr=57,bitfield=2,uninit
	_SROFT_2 .ds 1
	.ends

	_SROFT_3_SysRegDefine.c .section bank0,addr=57,bitfield=3,uninit
	_SROFT_3 .ds 1
	.ends

	_SROFT_4_SysRegDefine.c .section bank0,addr=57,bitfield=4,uninit
	_SROFT_4 .ds 1
	.ends

	_SROFT_5_SysRegDefine.c .section bank0,addr=57,bitfield=5,uninit
	_SROFT_5 .ds 1
	.ends

	_SROFT_6_SysRegDefine.c .section bank0,addr=57,bitfield=6,uninit
	_SROFT_6 .ds 1
	.ends

	_SROFT_7_SysRegDefine.c .section bank0,addr=57,bitfield=7,uninit
	_SROFT_7 .ds 1
	.ends

	_SROFT_8_SysRegDefine.c .section bank0,addr=58,bitfield=0,uninit
	_SROFT_8 .ds 1
	.ends

	_SROFT_9_SysRegDefine.c .section bank0,addr=58,bitfield=1,uninit
	_SROFT_9 .ds 1
	.ends

	_SROFT_10_SysRegDefine.c .section bank0,addr=58,bitfield=2,uninit
	_SROFT_10 .ds 1
	.ends

	_SROFT_11_SysRegDefine.c .section bank0,addr=58,bitfield=3,uninit
	_SROFT_11 .ds 1
	.ends

	_UR0IF_SysRegDefine.c .section bank0,addr=60,bitfield=0,uninit
	_UR0IF .ds 1
	.ends

	_I2CIF_SysRegDefine.c .section bank0,addr=60,bitfield=1,uninit
	_I2CIF .ds 1
	.ends

	_LVDIF_SysRegDefine.c .section bank0,addr=60,bitfield=2,uninit
	_LVDIF .ds 1
	.ends

	_TM4IF_SysRegDefine.c .section bank0,addr=60,bitfield=3,uninit
	_TM4IF .ds 1
	.ends

	_TM3IF_SysRegDefine.c .section bank0,addr=60,bitfield=4,uninit
	_TM3IF .ds 1
	.ends

	_LVDIE_SysRegDefine.c .section bank0,addr=61,bitfield=2,uninit
	_LVDIE .ds 1
	.ends

	_TM4IE_SysRegDefine.c .section bank0,addr=61,bitfield=3,uninit
	_TM4IE .ds 1
	.ends

	_TM3IE_SysRegDefine.c .section bank0,addr=61,bitfield=4,uninit
	_TM3IE .ds 1
	.ends

	_INTCFG_0_SysRegDefine.c .section bank0,addr=64,bitfield=0,uninit
	_INTCFG_0 .ds 1
	.ends

	_INTCFG_1_SysRegDefine.c .section bank0,addr=64,bitfield=1,uninit
	_INTCFG_1 .ds 1
	.ends

	_INTCFG_2_SysRegDefine.c .section bank0,addr=64,bitfield=2,uninit
	_INTCFG_2 .ds 1
	.ends

	_INTCFG_3_SysRegDefine.c .section bank0,addr=64,bitfield=3,uninit
	_INTCFG_3 .ds 1
	.ends

	_INTCFG_4_SysRegDefine.c .section bank0,addr=64,bitfield=4,uninit
	_INTCFG_4 .ds 1
	.ends

	_INTCFG_5_SysRegDefine.c .section bank0,addr=64,bitfield=5,uninit
	_INTCFG_5 .ds 1
	.ends

	_INTCFG_6_SysRegDefine.c .section bank0,addr=64,bitfield=6,uninit
	_INTCFG_6 .ds 1
	.ends

	_INTCFG_7_SysRegDefine.c .section bank0,addr=64,bitfield=7,uninit
	_INTCFG_7 .ds 1
	.ends

	_PT1CON0_SysRegDefine.c .section bank0,addr=65,bitfield=0,uninit
	_PT1CON0 .ds 1
	.ends

	_PT5W_5_SysRegDefine.c .section bank0,addr=66,bitfield=5,uninit
	_PT5W_5 .ds 1
	.ends

	_PT5W_6_SysRegDefine.c .section bank0,addr=66,bitfield=6,uninit
	_PT5W_6 .ds 1
	.ends

	_PT5W_7_SysRegDefine.c .section bank0,addr=66,bitfield=7,uninit
	_PT5W_7 .ds 1
	.ends

	_P3L2OEN_SysRegDefine.c .section bank0,addr=69,bitfield=0,uninit
	_P3L2OEN .ds 1
	.ends

	_P3H2OEN_SysRegDefine.c .section bank0,addr=69,bitfield=1,uninit
	_P3H2OEN .ds 1
	.ends

	_P3L2INV_SysRegDefine.c .section bank0,addr=69,bitfield=2,uninit
	_P3L2INV .ds 1
	.ends

	_P3H2INV_SysRegDefine.c .section bank0,addr=69,bitfield=3,uninit
	_P3H2INV .ds 1
	.ends

	_PWM3PO_SysRegDefine.c .section bank0,addr=69,bitfield=7,uninit
	_PWM3PO .ds 1
	.ends

	_TR_0_SysRegDefine.c .section bank0,addr=71,bitfield=0,uninit
	_TR_0 .ds 1
	.ends

	_TR_1_SysRegDefine.c .section bank0,addr=71,bitfield=1,uninit
	_TR_1 .ds 1
	.ends

	_TR_2_SysRegDefine.c .section bank0,addr=71,bitfield=2,uninit
	_TR_2 .ds 1
	.ends

	_TR_3_SysRegDefine.c .section bank0,addr=71,bitfield=3,uninit
	_TR_3 .ds 1
	.ends

	_TR_4_SysRegDefine.c .section bank0,addr=71,bitfield=4,uninit
	_TR_4 .ds 1
	.ends

	_TR_5_SysRegDefine.c .section bank0,addr=71,bitfield=5,uninit
	_TR_5 .ds 1
	.ends

	_TR_6_SysRegDefine.c .section bank0,addr=71,bitfield=6,uninit
	_TR_6 .ds 1
	.ends

	_WWDTEN_SysRegDefine.c .section bank0,addr=71,bitfield=7,uninit
	_WWDTEN .ds 1
	.ends

	_WD_0_SysRegDefine.c .section bank0,addr=72,bitfield=0,uninit
	_WD_0 .ds 1
	.ends

	_WD_1_SysRegDefine.c .section bank0,addr=72,bitfield=1,uninit
	_WD_1 .ds 1
	.ends

	_WD_2_SysRegDefine.c .section bank0,addr=72,bitfield=2,uninit
	_WD_2 .ds 1
	.ends

	_WD_3_SysRegDefine.c .section bank0,addr=72,bitfield=3,uninit
	_WD_3 .ds 1
	.ends

	_WD_4_SysRegDefine.c .section bank0,addr=72,bitfield=4,uninit
	_WD_4 .ds 1
	.ends

	_WD_5_SysRegDefine.c .section bank0,addr=72,bitfield=5,uninit
	_WD_5 .ds 1
	.ends

	_WD_6_SysRegDefine.c .section bank0,addr=72,bitfield=6,uninit
	_WD_6 .ds 1
	.ends

	_UART0_EN_SysRegDefine.c .section bank0,addr=80,bitfield=0,uninit
	_UART0_EN .ds 1
	.ends

	_UART0_SEL_SysRegDefine.c .section bank0,addr=80,bitfield=1,uninit
	_UART0_SEL .ds 1
	.ends

	_TX_EN_SysRegDefine.c .section bank0,addr=80,bitfield=2,uninit
	_TX_EN .ds 1
	.ends

	_RX_EN_SysRegDefine.c .section bank0,addr=80,bitfield=3,uninit
	_RX_EN .ds 1
	.ends

	_RX9_EN_SysRegDefine.c .section bank0,addr=80,bitfield=4,uninit
	_RX9_EN .ds 1
	.ends

	_TX9_EN_SysRegDefine.c .section bank0,addr=80,bitfield=5,uninit
	_TX9_EN .ds 1
	.ends

	_RX9D_SysRegDefine.c .section bank0,addr=80,bitfield=6,uninit
	_RX9D .ds 1
	.ends

	_TX9D_SysRegDefine.c .section bank0,addr=80,bitfield=7,uninit
	_TX9D .ds 1
	.ends

	_BRR0_0_SysRegDefine.c .section bank0,addr=81,bitfield=0,uninit
	_BRR0_0 .ds 1
	.ends

	_BRR0_1_SysRegDefine.c .section bank0,addr=81,bitfield=1,uninit
	_BRR0_1 .ds 1
	.ends

	_BRR0_2_SysRegDefine.c .section bank0,addr=81,bitfield=2,uninit
	_BRR0_2 .ds 1
	.ends

	_BRR0_3_SysRegDefine.c .section bank0,addr=81,bitfield=3,uninit
	_BRR0_3 .ds 1
	.ends

	_BRR0_4_SysRegDefine.c .section bank0,addr=81,bitfield=4,uninit
	_BRR0_4 .ds 1
	.ends

	_BRR0_5_SysRegDefine.c .section bank0,addr=81,bitfield=5,uninit
	_BRR0_5 .ds 1
	.ends

	_BRR0_6_SysRegDefine.c .section bank0,addr=81,bitfield=6,uninit
	_BRR0_6 .ds 1
	.ends

	_BRR0_7_SysRegDefine.c .section bank0,addr=81,bitfield=7,uninit
	_BRR0_7 .ds 1
	.ends

	_BRR1_0_SysRegDefine.c .section bank0,addr=82,bitfield=0,uninit
	_BRR1_0 .ds 1
	.ends

	_BRR1_1_SysRegDefine.c .section bank0,addr=82,bitfield=1,uninit
	_BRR1_1 .ds 1
	.ends

	_BRR1_2_SysRegDefine.c .section bank0,addr=82,bitfield=2,uninit
	_BRR1_2 .ds 1
	.ends

	_BRR1_3_SysRegDefine.c .section bank0,addr=82,bitfield=3,uninit
	_BRR1_3 .ds 1
	.ends

	_UARTDIV_0_SysRegDefine.c .section bank0,addr=82,bitfield=4,uninit
	_UARTDIV_0 .ds 1
	.ends

	_UARTDIV_1_SysRegDefine.c .section bank0,addr=82,bitfield=5,uninit
	_UARTDIV_1 .ds 1
	.ends

	_UARTDIV_2_SysRegDefine.c .section bank0,addr=82,bitfield=6,uninit
	_UARTDIV_2 .ds 1
	.ends

	_TX_REG_0_SysRegDefine.c .section bank0,addr=83,bitfield=0,uninit
	_TX_REG_0 .ds 1
	.ends

	_TX_REG_1_SysRegDefine.c .section bank0,addr=83,bitfield=1,uninit
	_TX_REG_1 .ds 1
	.ends

	_TX_REG_2_SysRegDefine.c .section bank0,addr=83,bitfield=2,uninit
	_TX_REG_2 .ds 1
	.ends

	_TX_REG_3_SysRegDefine.c .section bank0,addr=83,bitfield=3,uninit
	_TX_REG_3 .ds 1
	.ends

	_TX_REG_4_SysRegDefine.c .section bank0,addr=83,bitfield=4,uninit
	_TX_REG_4 .ds 1
	.ends

	_TX_REG_5_SysRegDefine.c .section bank0,addr=83,bitfield=5,uninit
	_TX_REG_5 .ds 1
	.ends

	_TX_REG_6_SysRegDefine.c .section bank0,addr=83,bitfield=6,uninit
	_TX_REG_6 .ds 1
	.ends

	_TX_REG_7_SysRegDefine.c .section bank0,addr=83,bitfield=7,uninit
	_TX_REG_7 .ds 1
	.ends

	_RX_REG_0_SysRegDefine.c .section bank0,addr=84,bitfield=0,uninit
	_RX_REG_0 .ds 1
	.ends

	_RX_REG_1_SysRegDefine.c .section bank0,addr=84,bitfield=1,uninit
	_RX_REG_1 .ds 1
	.ends

	_RX_REG_2_SysRegDefine.c .section bank0,addr=84,bitfield=2,uninit
	_RX_REG_2 .ds 1
	.ends

	_RX_REG_3_SysRegDefine.c .section bank0,addr=84,bitfield=3,uninit
	_RX_REG_3 .ds 1
	.ends

	_RX_REG_4_SysRegDefine.c .section bank0,addr=84,bitfield=4,uninit
	_RX_REG_4 .ds 1
	.ends

	_RX_REG_5_SysRegDefine.c .section bank0,addr=84,bitfield=5,uninit
	_RX_REG_5 .ds 1
	.ends

	_RX_REG_6_SysRegDefine.c .section bank0,addr=84,bitfield=6,uninit
	_RX_REG_6 .ds 1
	.ends

	_RX_REG_7_SysRegDefine.c .section bank0,addr=84,bitfield=7,uninit
	_RX_REG_7 .ds 1
	.ends

	_STOP_ERR_SysRegDefine.c .section bank0,addr=85,bitfield=0,uninit
	_STOP_ERR .ds 1
	.ends

	_RX_OV_ERR_SysRegDefine.c .section bank0,addr=85,bitfield=1,uninit
	_RX_OV_ERR .ds 1
	.ends

	_TX_BUSY_SysRegDefine.c .section bank0,addr=85,bitfield=2,uninit
	_TX_BUSY .ds 1
	.ends

	_RX_BUSY_SysRegDefine.c .section bank0,addr=85,bitfield=3,uninit
	_RX_BUSY .ds 1
	.ends

	_TXFIFO_EMPTY_SysRegDefine.c .section bank0,addr=85,bitfield=4,uninit
	_TXFIFO_EMPTY .ds 1
	.ends

	_UR_RINV_SysRegDefine.c .section bank0,addr=85,bitfield=6,uninit
	_UR_RINV .ds 1
	.ends

	_UR_TINV_SysRegDefine.c .section bank0,addr=85,bitfield=7,uninit
	_UR_TINV .ds 1
	.ends

	_UR0_TEIF_SysRegDefine.c .section bank0,addr=86,bitfield=0,uninit
	_UR0_TEIF .ds 1
	.ends

	_UR0WK_IF_SysRegDefine.c .section bank0,addr=86,bitfield=1,uninit
	_UR0WK_IF .ds 1
	.ends

	_UR0_RNIF_SysRegDefine.c .section bank0,addr=86,bitfield=2,uninit
	_UR0_RNIF .ds 1
	.ends

	_UR0_RHIF_SysRegDefine.c .section bank0,addr=86,bitfield=3,uninit
	_UR0_RHIF .ds 1
	.ends

	_UR0ERRIF_SysRegDefine.c .section bank0,addr=86,bitfield=4,uninit
	_UR0ERRIF .ds 1
	.ends

	_UR0_TEIE_SysRegDefine.c .section bank0,addr=87,bitfield=0,uninit
	_UR0_TEIE .ds 1
	.ends

	_UR0WK_IE_SysRegDefine.c .section bank0,addr=87,bitfield=1,uninit
	_UR0WK_IE .ds 1
	.ends

	_UR0_RNIE_SysRegDefine.c .section bank0,addr=87,bitfield=2,uninit
	_UR0_RNIE .ds 1
	.ends

	_UR0_RHIE_SysRegDefine.c .section bank0,addr=87,bitfield=3,uninit
	_UR0_RHIE .ds 1
	.ends

	_UR0ERRIE_SysRegDefine.c .section bank0,addr=87,bitfield=4,uninit
	_UR0ERRIE .ds 1
	.ends

	_I2CSTUS_0_SysRegDefine.c .section bank0,addr=89,bitfield=0,uninit
	_I2CSTUS_0 .ds 1
	.ends

	_I2CSTUS_1_SysRegDefine.c .section bank0,addr=89,bitfield=1,uninit
	_I2CSTUS_1 .ds 1
	.ends

	_I2CSTUS_2_SysRegDefine.c .section bank0,addr=89,bitfield=2,uninit
	_I2CSTUS_2 .ds 1
	.ends

	_I2CSTUS_3_SysRegDefine.c .section bank0,addr=89,bitfield=3,uninit
	_I2CSTUS_3 .ds 1
	.ends

	_ACK_EN_SysRegDefine.c .section bank0,addr=89,bitfield=4,uninit
	_ACK_EN .ds 1
	.ends

	_CST_EN_SysRegDefine.c .section bank0,addr=89,bitfield=5,uninit
	_CST_EN .ds 1
	.ends

	_AWK_EN_SysRegDefine.c .section bank0,addr=89,bitfield=6,uninit
	_AWK_EN .ds 1
	.ends

	_I2C_EN_SysRegDefine.c .section bank0,addr=89,bitfield=7,uninit
	_I2C_EN .ds 1
	.ends

	_I2C_DIV_0_SysRegDefine.c .section bank0,addr=90,bitfield=0,uninit
	_I2C_DIV_0 .ds 1
	.ends

	_I2C_DIV_1_SysRegDefine.c .section bank0,addr=90,bitfield=1,uninit
	_I2C_DIV_1 .ds 1
	.ends

	_I2C_SEL_SysRegDefine.c .section bank0,addr=90,bitfield=7,uninit
	_I2C_SEL .ds 1
	.ends

	_I2CDAT_0_SysRegDefine.c .section bank0,addr=91,bitfield=0,uninit
	_I2CDAT_0 .ds 1
	.ends

	_I2CDAT_1_SysRegDefine.c .section bank0,addr=91,bitfield=1,uninit
	_I2CDAT_1 .ds 1
	.ends

	_I2CDAT_2_SysRegDefine.c .section bank0,addr=91,bitfield=2,uninit
	_I2CDAT_2 .ds 1
	.ends

	_I2CDAT_3_SysRegDefine.c .section bank0,addr=91,bitfield=3,uninit
	_I2CDAT_3 .ds 1
	.ends

	_I2CDAT_4_SysRegDefine.c .section bank0,addr=91,bitfield=4,uninit
	_I2CDAT_4 .ds 1
	.ends

	_I2CDAT_5_SysRegDefine.c .section bank0,addr=91,bitfield=5,uninit
	_I2CDAT_5 .ds 1
	.ends

	_I2CDAT_6_SysRegDefine.c .section bank0,addr=91,bitfield=6,uninit
	_I2CDAT_6 .ds 1
	.ends

	_I2CDAT_7_SysRegDefine.c .section bank0,addr=91,bitfield=7,uninit
	_I2CDAT_7 .ds 1
	.ends

	_GC_EN_SysRegDefine.c .section bank0,addr=92,bitfield=0,uninit
	_GC_EN .ds 1
	.ends

	_I2CADR_0_SysRegDefine.c .section bank0,addr=92,bitfield=1,uninit
	_I2CADR_0 .ds 1
	.ends

	_I2CADR_1_SysRegDefine.c .section bank0,addr=92,bitfield=2,uninit
	_I2CADR_1 .ds 1
	.ends

	_I2CADR_2_SysRegDefine.c .section bank0,addr=92,bitfield=3,uninit
	_I2CADR_2 .ds 1
	.ends

	_I2CADR_3_SysRegDefine.c .section bank0,addr=92,bitfield=4,uninit
	_I2CADR_3 .ds 1
	.ends

	_I2CADR_4_SysRegDefine.c .section bank0,addr=92,bitfield=5,uninit
	_I2CADR_4 .ds 1
	.ends

	_I2CADR_5_SysRegDefine.c .section bank0,addr=92,bitfield=6,uninit
	_I2CADR_5 .ds 1
	.ends

	_I2CADR_6_SysRegDefine.c .section bank0,addr=92,bitfield=7,uninit
	_I2CADR_6 .ds 1
	.ends

	_I2C_STIF_SysRegDefine.c .section bank0,addr=93,bitfield=5,uninit
	_I2C_STIF .ds 1
	.ends

	_I2C_RIF_SysRegDefine.c .section bank0,addr=93,bitfield=6,uninit
	_I2C_RIF .ds 1
	.ends

	_I2C_TIF_SysRegDefine.c .section bank0,addr=93,bitfield=7,uninit
	_I2C_TIF .ds 1
	.ends

	_I2C_STIE_SysRegDefine.c .section bank0,addr=94,bitfield=5,uninit
	_I2C_STIE .ds 1
	.ends

	_I2C_RIE_SysRegDefine.c .section bank0,addr=94,bitfield=6,uninit
	_I2C_RIE .ds 1
	.ends

	_I2C_TIE_SysRegDefine.c .section bank0,addr=94,bitfield=7,uninit
	_I2C_TIE .ds 1
	.ends

	_ISPOF_SysRegDefine.c .section bank0,addr=96,bitfield=0,uninit
	_ISPOF .ds 1
	.ends

	_ISPWDTRF_SysRegDefine.c .section bank0,addr=96,bitfield=6,uninit
	_ISPWDTRF .ds 1
	.ends

	_WRPRTF_SysRegDefine.c .section bank0,addr=99,bitfield=0,uninit
	_WRPRTF .ds 1
	.ends

	_PWM4OUT_SysRegDefine.c .section bank0,addr=100,bitfield=0,uninit
	_PWM4OUT .ds 1
	.ends

	_T4OUT_SysRegDefine.c .section bank0,addr=100,bitfield=1,uninit
	_T4OUT .ds 1
	.ends

	_T4RSTB_SysRegDefine.c .section bank0,addr=100,bitfield=2,uninit
	_T4RSTB .ds 1
	.ends

	_T4CKS_SysRegDefine.c .section bank0,addr=100,bitfield=3,uninit
	_T4CKS .ds 1
	.ends

	_T4RATE_0_SysRegDefine.c .section bank0,addr=100,bitfield=4,uninit
	_T4RATE_0 .ds 1
	.ends

	_T4RATE_1_SysRegDefine.c .section bank0,addr=100,bitfield=5,uninit
	_T4RATE_1 .ds 1
	.ends

	_T4RATE_2_SysRegDefine.c .section bank0,addr=100,bitfield=6,uninit
	_T4RATE_2 .ds 1
	.ends

	_T4EN_SysRegDefine.c .section bank0,addr=100,bitfield=7,uninit
	_T4EN .ds 1
	.ends

	_TM4IN_0_SysRegDefine.c .section bank0,addr=101,bitfield=0,uninit
	_TM4IN_0 .ds 1
	.ends

	_TM4IN_1_SysRegDefine.c .section bank0,addr=101,bitfield=1,uninit
	_TM4IN_1 .ds 1
	.ends

	_TM4IN_2_SysRegDefine.c .section bank0,addr=101,bitfield=2,uninit
	_TM4IN_2 .ds 1
	.ends

	_TM4IN_3_SysRegDefine.c .section bank0,addr=101,bitfield=3,uninit
	_TM4IN_3 .ds 1
	.ends

	_TM4IN_4_SysRegDefine.c .section bank0,addr=101,bitfield=4,uninit
	_TM4IN_4 .ds 1
	.ends

	_TM4IN_5_SysRegDefine.c .section bank0,addr=101,bitfield=5,uninit
	_TM4IN_5 .ds 1
	.ends

	_TM4IN_6_SysRegDefine.c .section bank0,addr=101,bitfield=6,uninit
	_TM4IN_6 .ds 1
	.ends

	_TM4IN_7_SysRegDefine.c .section bank0,addr=101,bitfield=7,uninit
	_TM4IN_7 .ds 1
	.ends

	_TM4CNT_0_SysRegDefine.c .section bank0,addr=102,bitfield=0,uninit
	_TM4CNT_0 .ds 1
	.ends

	_TM4CNT_1_SysRegDefine.c .section bank0,addr=102,bitfield=1,uninit
	_TM4CNT_1 .ds 1
	.ends

	_TM4CNT_2_SysRegDefine.c .section bank0,addr=102,bitfield=2,uninit
	_TM4CNT_2 .ds 1
	.ends

	_TM4CNT_3_SysRegDefine.c .section bank0,addr=102,bitfield=3,uninit
	_TM4CNT_3 .ds 1
	.ends

	_TM4CNT_4_SysRegDefine.c .section bank0,addr=102,bitfield=4,uninit
	_TM4CNT_4 .ds 1
	.ends

	_TM4CNT_5_SysRegDefine.c .section bank0,addr=102,bitfield=5,uninit
	_TM4CNT_5 .ds 1
	.ends

	_TM4CNT_6_SysRegDefine.c .section bank0,addr=102,bitfield=6,uninit
	_TM4CNT_6 .ds 1
	.ends

	_TM4CNT_7_SysRegDefine.c .section bank0,addr=102,bitfield=7,uninit
	_TM4CNT_7 .ds 1
	.ends

	_TM4R_0_SysRegDefine.c .section bank0,addr=103,bitfield=0,uninit
	_TM4R_0 .ds 1
	.ends

	_TM4R_1_SysRegDefine.c .section bank0,addr=103,bitfield=1,uninit
	_TM4R_1 .ds 1
	.ends

	_TM4R_2_SysRegDefine.c .section bank0,addr=103,bitfield=2,uninit
	_TM4R_2 .ds 1
	.ends

	_TM4R_3_SysRegDefine.c .section bank0,addr=103,bitfield=3,uninit
	_TM4R_3 .ds 1
	.ends

	_TM4R_4_SysRegDefine.c .section bank0,addr=103,bitfield=4,uninit
	_TM4R_4 .ds 1
	.ends

	_TM4R_5_SysRegDefine.c .section bank0,addr=103,bitfield=5,uninit
	_TM4R_5 .ds 1
	.ends

	_TM4R_6_SysRegDefine.c .section bank0,addr=103,bitfield=6,uninit
	_TM4R_6 .ds 1
	.ends

	_TM4R_7_SysRegDefine.c .section bank0,addr=103,bitfield=7,uninit
	_TM4R_7 .ds 1
	.ends

	_TM4IN_8_SysRegDefine.c .section bank0,addr=104,bitfield=0,uninit
	_TM4IN_8 .ds 1
	.ends

	_TM4IN_9_SysRegDefine.c .section bank0,addr=104,bitfield=1,uninit
	_TM4IN_9 .ds 1
	.ends

	_TM4IN_10_SysRegDefine.c .section bank0,addr=104,bitfield=2,uninit
	_TM4IN_10 .ds 1
	.ends

	_TM4IN_11_SysRegDefine.c .section bank0,addr=104,bitfield=3,uninit
	_TM4IN_11 .ds 1
	.ends

	_TM4CNT_8_SysRegDefine.c .section bank0,addr=105,bitfield=0,uninit
	_TM4CNT_8 .ds 1
	.ends

	_TM4CNT_9_SysRegDefine.c .section bank0,addr=105,bitfield=1,uninit
	_TM4CNT_9 .ds 1
	.ends

	_TM4CNT_10_SysRegDefine.c .section bank0,addr=105,bitfield=2,uninit
	_TM4CNT_10 .ds 1
	.ends

	_TM4CNT_11_SysRegDefine.c .section bank0,addr=105,bitfield=3,uninit
	_TM4CNT_11 .ds 1
	.ends

	_TM4R_8_SysRegDefine.c .section bank0,addr=106,bitfield=0,uninit
	_TM4R_8 .ds 1
	.ends

	_TM4R_9_SysRegDefine.c .section bank0,addr=106,bitfield=1,uninit
	_TM4R_9 .ds 1
	.ends

	_TM4R_10_SysRegDefine.c .section bank0,addr=106,bitfield=2,uninit
	_TM4R_10 .ds 1
	.ends

	_TM4R_11_SysRegDefine.c .section bank0,addr=106,bitfield=3,uninit
	_TM4R_11 .ds 1
	.ends

	_LEDADR_0_SysRegDefine.c .section bank0,addr=110,bitfield=0,uninit
	_LEDADR_0 .ds 1
	.ends

	_LEDADR_1_SysRegDefine.c .section bank0,addr=110,bitfield=1,uninit
	_LEDADR_1 .ds 1
	.ends

	_LEDADR_2_SysRegDefine.c .section bank0,addr=110,bitfield=2,uninit
	_LEDADR_2 .ds 1
	.ends

	_LEDDAT_0_SysRegDefine.c .section bank0,addr=111,bitfield=0,uninit
	_LEDDAT_0 .ds 1
	.ends

	_LEDDAT_1_SysRegDefine.c .section bank0,addr=111,bitfield=1,uninit
	_LEDDAT_1 .ds 1
	.ends

	_LEDDAT_2_SysRegDefine.c .section bank0,addr=111,bitfield=2,uninit
	_LEDDAT_2 .ds 1
	.ends

	_LEDDAT_3_SysRegDefine.c .section bank0,addr=111,bitfield=3,uninit
	_LEDDAT_3 .ds 1
	.ends

	_LEDDAT_4_SysRegDefine.c .section bank0,addr=111,bitfield=4,uninit
	_LEDDAT_4 .ds 1
	.ends

	_LEDDAT_5_SysRegDefine.c .section bank0,addr=111,bitfield=5,uninit
	_LEDDAT_5 .ds 1
	.ends

	_LEDDAT_6_SysRegDefine.c .section bank0,addr=111,bitfield=6,uninit
	_LEDDAT_6 .ds 1
	.ends

	_LEDDAT_7_SysRegDefine.c .section bank0,addr=111,bitfield=7,uninit
	_LEDDAT_7 .ds 1
	.ends

	_LEDDUTY_0_SysRegDefine.c .section bank0,addr=112,bitfield=0,uninit
	_LEDDUTY_0 .ds 1
	.ends

	_LEDDUTY_1_SysRegDefine.c .section bank0,addr=112,bitfield=1,uninit
	_LEDDUTY_1 .ds 1
	.ends

	_LEDDUTY_2_SysRegDefine.c .section bank0,addr=112,bitfield=2,uninit
	_LEDDUTY_2 .ds 1
	.ends

	_LEDDUTY_3_SysRegDefine.c .section bank0,addr=112,bitfield=3,uninit
	_LEDDUTY_3 .ds 1
	.ends

	_LEDDUTY_4_SysRegDefine.c .section bank0,addr=112,bitfield=4,uninit
	_LEDDUTY_4 .ds 1
	.ends

	_LEDCOM_0_SysRegDefine.c .section bank0,addr=113,bitfield=0,uninit
	_LEDCOM_0 .ds 1
	.ends

	_LEDCOM_1_SysRegDefine.c .section bank0,addr=113,bitfield=1,uninit
	_LEDCOM_1 .ds 1
	.ends

	_LEDCOM_2_SysRegDefine.c .section bank0,addr=113,bitfield=2,uninit
	_LEDCOM_2 .ds 1
	.ends

	_LEDCOM_3_SysRegDefine.c .section bank0,addr=113,bitfield=3,uninit
	_LEDCOM_3 .ds 1
	.ends

	_LEDCOM_4_SysRegDefine.c .section bank0,addr=113,bitfield=4,uninit
	_LEDCOM_4 .ds 1
	.ends

	_LEDCOM_5_SysRegDefine.c .section bank0,addr=113,bitfield=5,uninit
	_LEDCOM_5 .ds 1
	.ends

	_LEDCOM_6_SysRegDefine.c .section bank0,addr=113,bitfield=6,uninit
	_LEDCOM_6 .ds 1
	.ends

	_LEDCOM_7_SysRegDefine.c .section bank0,addr=113,bitfield=7,uninit
	_LEDCOM_7 .ds 1
	.ends

	_LEDNUM_0_SysRegDefine.c .section bank0,addr=114,bitfield=0,uninit
	_LEDNUM_0 .ds 1
	.ends

	_LEDNUM_1_SysRegDefine.c .section bank0,addr=114,bitfield=1,uninit
	_LEDNUM_1 .ds 1
	.ends

	_LEDAUTO_SysRegDefine.c .section bank0,addr=114,bitfield=4,uninit
	_LEDAUTO .ds 1
	.ends

	_LEDCKS_0_SysRegDefine.c .section bank0,addr=114,bitfield=5,uninit
	_LEDCKS_0 .ds 1
	.ends

	_LEDCKS_1_SysRegDefine.c .section bank0,addr=114,bitfield=6,uninit
	_LEDCKS_1 .ds 1
	.ends

	_LEDEN_SysRegDefine.c .section bank0,addr=114,bitfield=7,uninit
	_LEDEN .ds 1
	.ends

	_LEDCUR_0_SysRegDefine.c .section bank0,addr=115,bitfield=0,uninit
	_LEDCUR_0 .ds 1
	.ends

	_LEDCUR_1_SysRegDefine.c .section bank0,addr=115,bitfield=1,uninit
	_LEDCUR_1 .ds 1
	.ends

	_CHPBYPSS_SysRegDefine.c .section bank0,addr=116,bitfield=0,uninit
	_CHPBYPSS .ds 1
	.ends

	_CHPEN_SysRegDefine.c .section bank0,addr=116,bitfield=3,uninit
	_CHPEN .ds 1
	.ends

	_CHIPCLKSEL_0_SysRegDefine.c .section bank0,addr=116,bitfield=4,uninit
	_CHIPCLKSEL_0 .ds 1
	.ends

	_CHIPCLKSEL_1_SysRegDefine.c .section bank0,addr=116,bitfield=5,uninit
	_CHIPCLKSEL_1 .ds 1
	.ends

	_TBLPEN_0_SysRegDefine.c .section bank0,addr=119,bitfield=0,uninit
	_TBLPEN_0 .ds 1
	.ends

	_TBLPEN_1_SysRegDefine.c .section bank0,addr=119,bitfield=1,uninit
	_TBLPEN_1 .ds 1
	.ends

	_TBLPEN_2_SysRegDefine.c .section bank0,addr=119,bitfield=2,uninit
	_TBLPEN_2 .ds 1
	.ends

	_TBLPEN_3_SysRegDefine.c .section bank0,addr=119,bitfield=3,uninit
	_TBLPEN_3 .ds 1
	.ends

	_TBLPEN_4_SysRegDefine.c .section bank0,addr=119,bitfield=4,uninit
	_TBLPEN_4 .ds 1
	.ends

	_TBLPEN_5_SysRegDefine.c .section bank0,addr=119,bitfield=5,uninit
	_TBLPEN_5 .ds 1
	.ends

	_TBLPEN_6_SysRegDefine.c .section bank0,addr=119,bitfield=6,uninit
	_TBLPEN_6 .ds 1
	.ends

	_TBLPEN_7_SysRegDefine.c .section bank0,addr=119,bitfield=7,uninit
	_TBLPEN_7 .ds 1
	.ends

	_LVD_SEL_0_SysRegDefine.c .section bank0,addr=120,bitfield=0,uninit
	_LVD_SEL_0 .ds 1
	.ends

	_LVD_SEL_1_SysRegDefine.c .section bank0,addr=120,bitfield=1,uninit
	_LVD_SEL_1 .ds 1
	.ends

	_LVD_SEL_2_SysRegDefine.c .section bank0,addr=120,bitfield=2,uninit
	_LVD_SEL_2 .ds 1
	.ends

	_LVDF_SysRegDefine.c .section bank0,addr=120,bitfield=3,uninit
	_LVDF .ds 1
	.ends

	_LVDEN_SysRegDefine.c .section bank0,addr=120,bitfield=4,uninit
	_LVDEN .ds 1
	.ends

	_MCK1_0_SysRegDefine.c .section bank0,addr=121,bitfield=0,uninit
	_MCK1_0 .ds 1
	.ends

	_MCK1_1_SysRegDefine.c .section bank0,addr=121,bitfield=1,uninit
	_MCK1_1 .ds 1
	.ends

	_MCK1_2_SysRegDefine.c .section bank0,addr=121,bitfield=2,uninit
	_MCK1_2 .ds 1
	.ends

	_MCK1_3_SysRegDefine.c .section bank0,addr=121,bitfield=3,uninit
	_MCK1_3 .ds 1
	.ends

	_PT5_BIGDRV_0_SysRegDefine.c .section bank0,addr=122,bitfield=0,uninit
	_PT5_BIGDRV_0 .ds 1
	.ends

	_PT5_BIGDRV_1_SysRegDefine.c .section bank0,addr=122,bitfield=1,uninit
	_PT5_BIGDRV_1 .ds 1
	.ends

	_PT5_BIGDRV_2_SysRegDefine.c .section bank0,addr=122,bitfield=2,uninit
	_PT5_BIGDRV_2 .ds 1
	.ends

	_PT5_BIGDRV_3_SysRegDefine.c .section bank0,addr=122,bitfield=3,uninit
	_PT5_BIGDRV_3 .ds 1
	.ends

	_PT5_BIGDRV_4_SysRegDefine.c .section bank0,addr=122,bitfield=4,uninit
	_PT5_BIGDRV_4 .ds 1
	.ends

	_PT5_BIGDRV_5_SysRegDefine.c .section bank0,addr=122,bitfield=5,uninit
	_PT5_BIGDRV_5 .ds 1
	.ends

	_PT5_BIGDRV_6_SysRegDefine.c .section bank0,addr=122,bitfield=6,uninit
	_PT5_BIGDRV_6 .ds 1
	.ends

	_PT5_BIGDRV_7_SysRegDefine.c .section bank0,addr=122,bitfield=7,uninit
	_PT5_BIGDRV_7 .ds 1
	.ends

	_CONFLASH_0_SysRegDefine.c .section bank0,addr=124,bitfield=0,uninit
	_CONFLASH_0 .ds 1
	.ends

	_CONFLASH_1_SysRegDefine.c .section bank0,addr=124,bitfield=1,uninit
	_CONFLASH_1 .ds 1
	.ends

	_CONFLASH_2_SysRegDefine.c .section bank0,addr=124,bitfield=2,uninit
	_CONFLASH_2 .ds 1
	.ends

	_CONFLASH_3_SysRegDefine.c .section bank0,addr=124,bitfield=3,uninit
	_CONFLASH_3 .ds 1
	.ends

	_CONFLASH_4_SysRegDefine.c .section bank0,addr=124,bitfield=4,uninit
	_CONFLASH_4 .ds 1
	.ends

	_CONFLASH_5_SysRegDefine.c .section bank0,addr=124,bitfield=5,uninit
	_CONFLASH_5 .ds 1
	.ends

	.global	_IND0
	.global	_FSR0
	.global	_STATUS
	.global	_WORK
	.global	_INTF
	.global	_INTE
	.global	_BSK
	.global	_RSTSR
	.global	_EADRH
	.global	_EADRL
	.global	_EDATH
	.global	_WDTCON
	.global	_WDTIN
	.global	_TM0CON
	.global	_TM0IN
	.global	_TM0CNT
	.global	_PAGECTL
	.global	_MCK
	.global	_TM2CON
	.global	_TM2IN
	.global	_TM2CNT
	.global	_TM2R
	.global	_TM3CON
	.global	_TM3IN
	.global	_TM3CNT
	.global	_TM3R
	.global	_TM3INH
	.global	_PT1
	.global	_PT1EN
	.global	_PT1PU
	.global	_PT1CON
	.global	_TM2INH
	.global	_TM2CNTH
	.global	_TM2RH
	.global	_TM3CNTH
	.global	_PT3
	.global	_PT3EN
	.global	_PT3PU
	.global	_PT3CON
	.global	_TM3RH
	.global	_TM3CON2
	.global	_CONFIG1
	.global	_CONFIG2
	.global	_PT5
	.global	_PT5EN
	.global	_PT5PU
	.global	_PT5CON
	.global	_SRADCON0
	.global	_SRADCON1
	.global	_SRADCON2
	.global	_SRADL
	.global	_SRADH
	.global	_SROFTL
	.global	_SROFTH
	.global	_INTF2
	.global	_INTE2
	.global	_INTCFG
	.global	_PT1CON1
	.global	_PT5CON1
	.global	_TM3CON3
	.global	_WWDTCR
	.global	_WWDTWR
	.global	_UR0_CR1
	.global	_UR0_BRR0
	.global	_UR0_BRR1
	.global	_UR0_TX_REG
	.global	_UR0_RX_REG
	.global	_UR0_ST
	.global	_UR0_INTF
	.global	_UR0_INTE
	.global	_I2CCON
	.global	_I2CCON1
	.global	_I2CDAT
	.global	_I2CADR
	.global	_I2C_INTF
	.global	_I2C_INTE
	.global	_ISPCON1
	.global	_WRPRT
	.global	_TM4CON
	.global	_TM4IN
	.global	_TM4CNT
	.global	_TM4R
	.global	_TM4INH
	.global	_TM4CNTH
	.global	_TM4RH
	.global	_LEDADR
	.global	_LEDDAT
	.global	_LEDDUTY
	.global	_LEDCOM
	.global	_LEDCON
	.global	_LEDCON1
	.global	_CHPCON
	.global	_TBLPEN
	.global	_LVDCON
	.global	_MCK1
	.global	_PT5_BIGDRV
	.global	_CONFLASH
	.global	_Z
	.global	_C
	.global	_DC
	.global	_TO
	.global	_PD
	.global	_E0IF
	.global	_E1IF
	.global	_SRADIF
	.global	_TM0IF
	.global	_TM2IF
	.global	_E0IE
	.global	_E1IE
	.global	_SRADIE
	.global	_TM0IE
	.global	_TM2IE
	.global	_GIE
	.global	_PAGE_0
	.global	_IRP0
	.global	_WWDTF
	.global	_ILOPF
	.global	_EMCF
	.global	_EADR_8
	.global	_EADR_9
	.global	_EADR_10
	.global	_EADR_11
	.global	_EADR_12
	.global	_EADR_13
	.global	_EADR_14
	.global	_EADR_15
	.global	_EADR_0
	.global	_EADR_1
	.global	_EADR_2
	.global	_EADR_3
	.global	_EADR_4
	.global	_EADR_5
	.global	_EADR_6
	.global	_EADR_7
	.global	_EDATH_0
	.global	_EDATH_1
	.global	_EDATH_2
	.global	_EDATH_3
	.global	_EDATH_4
	.global	_EDATH_5
	.global	_EDATH_6
	.global	_EDATH_7
	.global	_WTS_0
	.global	_WTS_1
	.global	_WTS_2
	.global	_WDTEN
	.global	_WDTIN_0
	.global	_WDTIN_1
	.global	_WDTIN_2
	.global	_WDTIN_3
	.global	_WDTIN_4
	.global	_WDTIN_5
	.global	_WDTIN_6
	.global	_WDTIN_7
	.global	_T0SEL_0
	.global	_T0SEL_1
	.global	_T0RSTB
	.global	_T0RATE_0
	.global	_T0RATE_1
	.global	_T0RATE_2
	.global	_T0EN
	.global	_TM0IN_0
	.global	_TM0IN_1
	.global	_TM0IN_2
	.global	_TM0IN_3
	.global	_TM0IN_4
	.global	_TM0IN_5
	.global	_TM0IN_6
	.global	_TM0IN_7
	.global	_TM0CNT_0
	.global	_TM0CNT_1
	.global	_TM0CNT_2
	.global	_TM0CNT_3
	.global	_TM0CNT_4
	.global	_TM0CNT_5
	.global	_TM0CNT_6
	.global	_TM0CNT_7
	.global	_PAGE2
	.global	_CST_WDT
	.global	_PWM2OUT
	.global	_T2OUT
	.global	_T2RSTB
	.global	_T2CKS
	.global	_T2RATE_0
	.global	_T2RATE_1
	.global	_T2RATE_2
	.global	_T2EN
	.global	_TM2IN_0
	.global	_TM2IN_1
	.global	_TM2IN_2
	.global	_TM2IN_3
	.global	_TM2IN_4
	.global	_TM2IN_5
	.global	_TM2IN_6
	.global	_TM2IN_7
	.global	_TM2CNT_0
	.global	_TM2CNT_1
	.global	_TM2CNT_2
	.global	_TM2CNT_3
	.global	_TM2CNT_4
	.global	_TM2CNT_5
	.global	_TM2CNT_6
	.global	_TM2CNT_7
	.global	_TM2R_0
	.global	_TM2R_1
	.global	_TM2R_2
	.global	_TM2R_3
	.global	_TM2R_4
	.global	_TM2R_5
	.global	_TM2R_6
	.global	_TM2R_7
	.global	_PWM3OUT
	.global	_T3OUT
	.global	_T3RSTB
	.global	_T3CKS
	.global	_T3RATE_0
	.global	_T3RATE_1
	.global	_T3RATE_2
	.global	_T3EN
	.global	_TM3IN_0
	.global	_TM3IN_1
	.global	_TM3IN_2
	.global	_TM3IN_3
	.global	_TM3IN_4
	.global	_TM3IN_5
	.global	_TM3IN_6
	.global	_TM3IN_7
	.global	_TM3CNT_0
	.global	_TM3CNT_1
	.global	_TM3CNT_2
	.global	_TM3CNT_3
	.global	_TM3CNT_4
	.global	_TM3CNT_5
	.global	_TM3CNT_6
	.global	_TM3CNT_7
	.global	_TM3R_0
	.global	_TM3R_1
	.global	_TM3R_2
	.global	_TM3R_3
	.global	_TM3R_4
	.global	_TM3R_5
	.global	_TM3R_6
	.global	_TM3R_7
	.global	_TM3INH_8
	.global	_TM3INH_9
	.global	_TM3INH_10
	.global	_TM3INH_11
	.global	_PT1_0
	.global	_PT1_3
	.global	_PT1_4
	.global	_PT1_5
	.global	_PT1EN_0
	.global	_PT1EN_3
	.global	_PT1EN_4
	.global	_PT1EN_5
	.global	_PT1PU_0
	.global	_PT1PU_3
	.global	_PT1PU_4
	.global	_PT1PU_5
	.global	_E0M_0
	.global	_E0M_1
	.global	_E1M
	.global	_PT1W_0
	.global	_PT1W_1
	.global	_PT1W_2
	.global	_TM2IN_8
	.global	_TM2IN_9
	.global	_TM2IN_10
	.global	_TM2IN_11
	.global	_TM2CNT_8
	.global	_TM2CNT_9
	.global	_TM2CNT_10
	.global	_TM2CNT_11
	.global	_TM2R_8
	.global	_TM2R_9
	.global	_TM2R_10
	.global	_TM2R_11
	.global	_TM3CNT_8
	.global	_TM3CNT_9
	.global	_TM3CNT_10
	.global	_TM3CNT_11
	.global	_PT3_0
	.global	_PT3_1
	.global	_PT3_2
	.global	_PT3_3
	.global	_PT3_4
	.global	_PT3_5
	.global	_PT3_6
	.global	_PT3EN_0
	.global	_PT3EN_1
	.global	_PT3EN_2
	.global	_PT3EN_3
	.global	_PT3EN_4
	.global	_PT3EN_5
	.global	_PT3EN_6
	.global	_PT3PU_0
	.global	_PT3PU_1
	.global	_PT3PU_2
	.global	_PT3PU_3
	.global	_PT3PU_4
	.global	_PT3PU_5
	.global	_PT3PU_6
	.global	_PT3CON_0
	.global	_PT3CON_1
	.global	_PT3CON_2
	.global	_PT3CON_3
	.global	_PT3CON_4
	.global	_PT3CON_5
	.global	_PT3CON_6
	.global	_TM3R_8
	.global	_TM3R_9
	.global	_TM3R_10
	.global	_TM3R_11
	.global	_P3L_OEN
	.global	_P3H_OEN
	.global	_DT3_EN
	.global	_DT3CNT_0
	.global	_DT3CNT_1
	.global	_DT3CNT_2
	.global	_DT3CK_0
	.global	_DT3CK_1
	.global	_PWM2PO
	.global	_PWM2STALL
	.global	_PWM3STALL
	.global	_PWM4STALL
	.global	_P3LINV
	.global	_P3HINV
	.global	_T4RATE_3
	.global	_T2RATE_3
	.global	_T3RATE_3
	.global	_PWMIS
	.global	_VTHSEL
	.global	_PT5_0
	.global	_PT5_1
	.global	_PT5_2
	.global	_PT5_3
	.global	_PT5_4
	.global	_PT5_5
	.global	_PT5_6
	.global	_PT5_7
	.global	_PT5EN_0
	.global	_PT5EN_1
	.global	_PT5EN_2
	.global	_PT5EN_3
	.global	_PT5EN_4
	.global	_PT5EN_5
	.global	_PT5EN_6
	.global	_PT5EN_7
	.global	_PT5PU_0
	.global	_PT5PU_1
	.global	_PT5PU_2
	.global	_PT5PU_3
	.global	_PT5PU_4
	.global	_PT5PU_5
	.global	_PT5PU_6
	.global	_PT5PU_7
	.global	_PT5CON_0
	.global	_PT5CON_1
	.global	_PT5CON_2
	.global	_PT5CON_3
	.global	_PT5CON_4
	.global	_PT5CON_5
	.global	_PT5CON_6
	.global	_PT5CON_7
	.global	_SRADCKS_0
	.global	_SRADCKS_1
	.global	_SRADACKS_0
	.global	_SRADACKS_1
	.global	_SARVCMSEL
	.global	_VREFS_0
	.global	_VREFS_1
	.global	_OFFEX
	.global	_ENOV
	.global	_CALIF
	.global	_OFTEN
	.global	_SRADS
	.global	_SRADEN
	.global	_SAR_DIFFEN
	.global	_CHS_0
	.global	_CHS_1
	.global	_CHS_2
	.global	_CHS_3
	.global	_SRAD_0
	.global	_SRAD_1
	.global	_SRAD_2
	.global	_SRAD_3
	.global	_SRAD_4
	.global	_SRAD_5
	.global	_SRAD_6
	.global	_SRAD_7
	.global	_SRAD_8
	.global	_SRAD_9
	.global	_SRAD_10
	.global	_SRAD_11
	.global	_SROFT_0
	.global	_SROFT_1
	.global	_SROFT_2
	.global	_SROFT_3
	.global	_SROFT_4
	.global	_SROFT_5
	.global	_SROFT_6
	.global	_SROFT_7
	.global	_SROFT_8
	.global	_SROFT_9
	.global	_SROFT_10
	.global	_SROFT_11
	.global	_UR0IF
	.global	_I2CIF
	.global	_LVDIF
	.global	_TM4IF
	.global	_TM3IF
	.global	_LVDIE
	.global	_TM4IE
	.global	_TM3IE
	.global	_INTCFG_0
	.global	_INTCFG_1
	.global	_INTCFG_2
	.global	_INTCFG_3
	.global	_INTCFG_4
	.global	_INTCFG_5
	.global	_INTCFG_6
	.global	_INTCFG_7
	.global	_PT1CON0
	.global	_PT5W_5
	.global	_PT5W_6
	.global	_PT5W_7
	.global	_P3L2OEN
	.global	_P3H2OEN
	.global	_P3L2INV
	.global	_P3H2INV
	.global	_PWM3PO
	.global	_TR_0
	.global	_TR_1
	.global	_TR_2
	.global	_TR_3
	.global	_TR_4
	.global	_TR_5
	.global	_TR_6
	.global	_WWDTEN
	.global	_WD_0
	.global	_WD_1
	.global	_WD_2
	.global	_WD_3
	.global	_WD_4
	.global	_WD_5
	.global	_WD_6
	.global	_UART0_EN
	.global	_UART0_SEL
	.global	_TX_EN
	.global	_RX_EN
	.global	_RX9_EN
	.global	_TX9_EN
	.global	_RX9D
	.global	_TX9D
	.global	_BRR0_0
	.global	_BRR0_1
	.global	_BRR0_2
	.global	_BRR0_3
	.global	_BRR0_4
	.global	_BRR0_5
	.global	_BRR0_6
	.global	_BRR0_7
	.global	_BRR1_0
	.global	_BRR1_1
	.global	_BRR1_2
	.global	_BRR1_3
	.global	_UARTDIV_0
	.global	_UARTDIV_1
	.global	_UARTDIV_2
	.global	_TX_REG_0
	.global	_TX_REG_1
	.global	_TX_REG_2
	.global	_TX_REG_3
	.global	_TX_REG_4
	.global	_TX_REG_5
	.global	_TX_REG_6
	.global	_TX_REG_7
	.global	_RX_REG_0
	.global	_RX_REG_1
	.global	_RX_REG_2
	.global	_RX_REG_3
	.global	_RX_REG_4
	.global	_RX_REG_5
	.global	_RX_REG_6
	.global	_RX_REG_7
	.global	_STOP_ERR
	.global	_RX_OV_ERR
	.global	_TX_BUSY
	.global	_RX_BUSY
	.global	_TXFIFO_EMPTY
	.global	_UR_RINV
	.global	_UR_TINV
	.global	_UR0_TEIF
	.global	_UR0WK_IF
	.global	_UR0_RNIF
	.global	_UR0_RHIF
	.global	_UR0ERRIF
	.global	_UR0_TEIE
	.global	_UR0WK_IE
	.global	_UR0_RNIE
	.global	_UR0_RHIE
	.global	_UR0ERRIE
	.global	_I2CSTUS_0
	.global	_I2CSTUS_1
	.global	_I2CSTUS_2
	.global	_I2CSTUS_3
	.global	_ACK_EN
	.global	_CST_EN
	.global	_AWK_EN
	.global	_I2C_EN
	.global	_I2C_DIV_0
	.global	_I2C_DIV_1
	.global	_I2C_SEL
	.global	_I2CDAT_0
	.global	_I2CDAT_1
	.global	_I2CDAT_2
	.global	_I2CDAT_3
	.global	_I2CDAT_4
	.global	_I2CDAT_5
	.global	_I2CDAT_6
	.global	_I2CDAT_7
	.global	_GC_EN
	.global	_I2CADR_0
	.global	_I2CADR_1
	.global	_I2CADR_2
	.global	_I2CADR_3
	.global	_I2CADR_4
	.global	_I2CADR_5
	.global	_I2CADR_6
	.global	_I2C_STIF
	.global	_I2C_RIF
	.global	_I2C_TIF
	.global	_I2C_STIE
	.global	_I2C_RIE
	.global	_I2C_TIE
	.global	_ISPOF
	.global	_ISPWDTRF
	.global	_WRPRTF
	.global	_PWM4OUT
	.global	_T4OUT
	.global	_T4RSTB
	.global	_T4CKS
	.global	_T4RATE_0
	.global	_T4RATE_1
	.global	_T4RATE_2
	.global	_T4EN
	.global	_TM4IN_0
	.global	_TM4IN_1
	.global	_TM4IN_2
	.global	_TM4IN_3
	.global	_TM4IN_4
	.global	_TM4IN_5
	.global	_TM4IN_6
	.global	_TM4IN_7
	.global	_TM4CNT_0
	.global	_TM4CNT_1
	.global	_TM4CNT_2
	.global	_TM4CNT_3
	.global	_TM4CNT_4
	.global	_TM4CNT_5
	.global	_TM4CNT_6
	.global	_TM4CNT_7
	.global	_TM4R_0
	.global	_TM4R_1
	.global	_TM4R_2
	.global	_TM4R_3
	.global	_TM4R_4
	.global	_TM4R_5
	.global	_TM4R_6
	.global	_TM4R_7
	.global	_TM4IN_8
	.global	_TM4IN_9
	.global	_TM4IN_10
	.global	_TM4IN_11
	.global	_TM4CNT_8
	.global	_TM4CNT_9
	.global	_TM4CNT_10
	.global	_TM4CNT_11
	.global	_TM4R_8
	.global	_TM4R_9
	.global	_TM4R_10
	.global	_TM4R_11
	.global	_LEDADR_0
	.global	_LEDADR_1
	.global	_LEDADR_2
	.global	_LEDDAT_0
	.global	_LEDDAT_1
	.global	_LEDDAT_2
	.global	_LEDDAT_3
	.global	_LEDDAT_4
	.global	_LEDDAT_5
	.global	_LEDDAT_6
	.global	_LEDDAT_7
	.global	_LEDDUTY_0
	.global	_LEDDUTY_1
	.global	_LEDDUTY_2
	.global	_LEDDUTY_3
	.global	_LEDDUTY_4
	.global	_LEDCOM_0
	.global	_LEDCOM_1
	.global	_LEDCOM_2
	.global	_LEDCOM_3
	.global	_LEDCOM_4
	.global	_LEDCOM_5
	.global	_LEDCOM_6
	.global	_LEDCOM_7
	.global	_LEDNUM_0
	.global	_LEDNUM_1
	.global	_LEDAUTO
	.global	_LEDCKS_0
	.global	_LEDCKS_1
	.global	_LEDEN
	.global	_LEDCUR_0
	.global	_LEDCUR_1
	.global	_CHPBYPSS
	.global	_CHPEN
	.global	_CHIPCLKSEL_0
	.global	_CHIPCLKSEL_1
	.global	_TBLPEN_0
	.global	_TBLPEN_1
	.global	_TBLPEN_2
	.global	_TBLPEN_3
	.global	_TBLPEN_4
	.global	_TBLPEN_5
	.global	_TBLPEN_6
	.global	_TBLPEN_7
	.global	_LVD_SEL_0
	.global	_LVD_SEL_1
	.global	_LVD_SEL_2
	.global	_LVDF
	.global	_LVDEN
	.global	_MCK1_0
	.global	_MCK1_1
	.global	_MCK1_2
	.global	_MCK1_3
	.global	_PT5_BIGDRV_0
	.global	_PT5_BIGDRV_1
	.global	_PT5_BIGDRV_2
	.global	_PT5_BIGDRV_3
	.global	_PT5_BIGDRV_4
	.global	_PT5_BIGDRV_5
	.global	_PT5_BIGDRV_6
	.global	_PT5_BIGDRV_7
	.global	_CONFLASH_0
	.global	_CONFLASH_1
	.global	_CONFLASH_2
	.global	_CONFLASH_3
	.global	_CONFLASH_4
	.global	_CONFLASH_5

